ASIC Physical implementation

I can't understand the stages of physical implementation (including syntheses, scan
insertion, PnR, timing and physical sign off).

Check this:
https://en.wikipedia.org/wiki/Physical_design_(electronics)

hi.........

Synthesis:- Synthesis is to transfer the RTL code to gate level (technology dependent).

Scan insertion:- The scan chain is an essential part of DFT strategy that improves a chip’s controllability and observability

PnR:- Placement and Routing
we place standard cells in the floorplan and the cells are routed.

Timing:- Timing is used to check the balance between data and the clock given at the correct time.

Physical Signoff:- It includes various steps like checking LVS and DRC errors...getting cdl,gds,lef,def files for the floorplan etc..

Well, the typical ASIC implementation stage involves other as well other than what you have written. In the industry, typically ASIC implementation involves the following:

1. PLDRC
* optional LVMEMBIST Insertion some companies prefer rtl level Membist insertion some prefer to insert in netlist
2. CDC
3. Synthesis
4. STA (pre-layout)
5. DFT (Scan-Insertion)
6. STA (with DFT information)
7. PD (here everything will happen like Floor planning, power planning, PG placement, Placement, pre-CTS, CTS, POst CTS, routing, EXtraction etc)
8. Followed by STA (post-layout)
9. GLS (Gate-level-simulation) with SDF (Standard Delay Format).
10. Final FV (Formal Verification). This is a very important step which happen, during all the stages of implementation after synthesis till PD netlist. Since, ECO comes into the picture thus is is necessary to perform FV.
11. Signoff
12.Tapeout
13. Then again GLS with ATPG once the silicon comes.


cheers

- - - Updated - - -

Well, the typical ASIC implementation stage involves other as well other than what you have written. In the industry, typically ASIC implementation involves the following:

1. PLDRC
* optional LVMEMBIST Insertion some companies prefer rtl level Membist insertion some prefer to insert in netlist
2. CDC
3. Synthesis
4. STA (pre-layout)
5. DFT (Scan-Insertion)
6. STA (with DFT information)
7. PD (here everything will happen like Floor planning, power planning, PG placement, Placement, pre-CTS, CTS, POst CTS, routing, EXtraction etc)
8. Followed by STA (post-layout)
9. GLS (Gate-level-simulation) with SDF (Standard Delay Format).
10. Final FV (Formal Verification). This is a very important step which happen, during all the stages of implementation after synthesis till PD netlist. Since, ECO comes into the picture thus is is necessary to perform FV.
11. Signoff
12.Tapeout
13. Then again GLS with ATPG once the silicon comes.


cheers