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ERROR:HDLParsers:164 - parse error, unexpected PORT, expecting OPENPAR or TICK or LS

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amisra24x7

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Dear everyone,

I am facing few syntax errors in my following code

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity verifier is
    Port ( clk		: in  std_logic;
           sum		: in  std_logic_vector(3 downto 0);
           cy		: in	std_logic;
           aout	: out std_logic_vector(3 downto 0);
           bout	: out std_logic_vector(3 downto 0);
			  cout	: out std_logic;
			  chkout : out std_logic_vector(7 downto 0));
end verifier;

architecture Behavioral of verifier is
				

				component full_adder
						Port(	a		: in	std_logic_vector(3 downto 0);
								b		: in	std_logic_vector(3 downto 0);
								cin	: in	std_logic;
								cout	: out std_logic;
								clk	: in	std_logic;
								s		: out	std_logic_vector(3 downto 0));
				end component;

				component comparator
						port(	a		:in	std_logic_vector(3 downto 0); 
								b		:in	std_logic_vector(3 downto 0);
								cin	:in	std_logic;
								clk	:in	std_logic;
								cout	:in	std_logic;
								s		:in	std_logic_vector(3 downto 0);
								chkr	:out	std_logic);
				end component;

begin

		process(clk)
				variable a_var,b_var	:	std_logic_vector(3 downto 0):="0000";
				variable chk,c_var		:	std_logic;
				variable chk_temp		:	std_logic_vector(7 downto 0);	

						begin
								a_count:for i in 15 downto 0 loop
												a_var:=a_var+1;

														b_count:for j in 15 downto 0 loop
																b_var:=b_var+1;
																		
																		cout_count:for k in 1 downto 0 loop
																				if(k=0) then
																				c_var:='0';
																				else c_var:='1';
																				end if;
																				aout<=a_var;
																				bout<=b_var;
																				cout<=c_var;
																				
																				fa :full_adder port map(aout,bout,cout,cy,clk,sum);            --Problem comes in this line
																				cmp:comparator port map(aout,bout,cout,clk,cy,sum,chk);  --Problem comes in this line
																						if(chk='1') then
																								chk_temp:=chk_temp+1;
																						end if;
																		end loop cout_count;
														end loop b_count;
								end loop a_count;
				chkout<=chk_temp;
		end process;

end Behavioral;

In the positions mentioned in the code, I face the following errors
Error.JPG

Kindly help me with the same.
If you'd like, you can mail the same to me.
If you wish to contact me with similar error, mail me at amisra24x7@gmail.com

Thank you,
Aditya Misra
 

Hi Aditya,

In your entity verifier the port cy is given as an input to the module. Then in the full_adder component mapping you mapped the input cy to the output port cout of the the full_adder. That wont allowed.
 

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