Problem using verilog-A to do simulation

Dear All,
I am learning how to use verilog-A to do simulation. I create a resistor by verilog-a:

the code is:

`include "constants.vams"
`include "disciplines.vams"

module resistor(p,n);

inout p,n;
electrical p,n;
parameter real r=1;

analog
V(p,n) <+ r*I(p,n);

endmodule

the schematic of my test bench is:


I followed the tutorial here:
**broken link removed**

the simulator I use is spectre, I also create a config file.

then when I simulate it in "analog environment", the simulation is successful but it seems there is no current flowing through the resistor.

What might be the problem?

Thanks for any suggestions!

Getting that probe current may need something done in
the port-mapping. Insert a trivial resistor or vdc=0 source
in series with the resistor and probe the current through
-that-. I've had to do this workaround before, never have
learned how to set that stuff up correctly.

Thank you, dick_freebird,
I will have a try~

- - - Updated - - -

It seems there is still no current....
I change the schematic into this:


And plot the current of the resistor, still zero...

This is really tough to set up...

Do you see messages about compiling the veriloga module? Is
veriloga view preceding symbol, schematic, etc. in the switch-
view list, or veriloga view selected in the hierarchy editor?
What happens if you make a schematic view with a resistor
(analogLib) inside, and then switch back & forth between
view choice in the hierarchy editor?

Thank you very much again, dick_freebird,
I will go check it.

By the way, do you think it may be the problem of license? I am not sure whether our Cadence can do verilog-A simulation.

- - - Updated - - -

Thank you, I do find the problem in the cmd window that tells me that the verilog-a is ignored:

pic

I will keep debugging this, any suggestions?

Best,

simon

Couple suggestions:

1. Check Environment (Setup/Environment/Switch View List). Must contain "veriloga"
2. Use resistor models from built in libraries: ahdlLib (veriloga model); and analogLib (spice model). See if you are able to probe currents/voltages/dc operating points.
If the result is still negative: check your library version with spectre version. The new spectre version (at least for mmsim10) is having difficulties with compilation of old veriloga models.

Good luck.