likewise
Newbie level 5
Hello all,
Suppose I have the following in SystemVerilog (intended to synthesize).
typedef packed struct begin
logic a;
logic b;
end mytype_t;
mytype_t myarray [1:100];
Is it possible to set field 'a' of all array members with a single assignment?
I understood from studying SV books it is possible to set a single dimension within a multidimensional array, and I would consider a field in a structure to be one dimension of my array.
I would expect something like this:
myarray.a <= 0;
myarray[].a <= 0;
myarray[0:100].a <= 0;
Regards,
Leon.
Suppose I have the following in SystemVerilog (intended to synthesize).
typedef packed struct begin
logic a;
logic b;
end mytype_t;
mytype_t myarray [1:100];
Is it possible to set field 'a' of all array members with a single assignment?
I understood from studying SV books it is possible to set a single dimension within a multidimensional array, and I would consider a field in a structure to be one dimension of my array.
I would expect something like this:
myarray.a <= 0;
myarray[].a <= 0;
myarray[0:100].a <= 0;
Regards,
Leon.