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how to compare at the end of the simulation time step

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tariq786

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Hi friends,

I want to compare two signals whenever one of them changes using if statement. But i want to do this comparison at the end of the simulation tick as one of them is a register and the other one is a wire.

Any ideas how to do it

always @(b)
//what should i put here to compare them at the end of the time step
begin
if( a == b)
$display("Pass");
else
$display("Fail");
end


Thanks
 

any one?

no response (REALLY!!)
 

Why is 'a' not in the sensitivity list? Based on your current code, when do you think is the comparison done? How are you modeling a register 'b' in verilog?
 
because i want to check the equality based on the change in b. a is stored in a register. As you know register assignment (Non blocking assignment) is done after wire (Blocking assignment),i want to do the comparison after the non blocking assignment. This means essentially at the end of the simulation time step.

Thanks for the post.
 

Try this,
Code: 
always @(b) begin
   $monitor("\n %s", (a==b)?"PASS":"FAIL"); 
end
 
Last edited:
Let me try.

Morris Mano thanks a lot dude.

Kind Regards,
tariq786
 

If you can use SystemVerilog, you should use an assertion to check this. Assertions always use sampled values (by default, at the beginning of the time step before any blocking or non-blocking assignments have executed).
 
$strobe is what i was looking for. Here is how it should be

always @(b) begin
$strobe("\n %s", (a==b)?"PASS":"FAIL");
end
 

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