XST 646 for Moving Average Filter

Hello Friends,
I am trying to design a moving average filter in FPGA. Using Xilinx Spartan 3A DSP XC3SD1800A.
I am getting XST 646 error. I am unable to locate the root of the problem.

I have tried to create an array of 12 bit word of length 2 to begin with. I am adding the 12 bit word and dividing by 2. But the RTL schematic is not showing a FIFO stack getting synthesized. It shows the error XST 646 avgA(0) not used or assigned. I have gone through the code again and again but failed to find the fault. I am posting the relevant portion of the code. Please help me.

Note:- signal count2 is a counter to execute the operations after a predefined clock cycles. signal "start" is used to fill the stack upto the desired length with fresh data(here length=2). After it is completely filled, FIFO action should continue.


entity Position_Estimator is
port( clk : in std_logic;
curr : in std_logic;
start_conv : in std_logic;
output : out std_logic_vector(11 downto 0);
A2 : out std_logic;
A1 : out std_logic;
A0 : out std_logic;
sclk : out std_logic;
sgl : out std_logic;
range1 : out std_logic;
cs : out std_logic);
end Position_Estimator;

architecture Position_Estimator of Position_Estimator is
signal xoutA:unsigned (11 downto 0):="000000000000";--
signal favg_A:integer range 0 to 4095:=0;
signal xcs,xsclk:std_logic;
signal count2:integer range 0 to 34:=0;
signal start : integer range 1 to 3:=1;
signal sumA: unsigned(12 downto 0):="0000000000000";

type FIFO is array (0 to 1) of unsigned(11 downto 0);
signal avgA:FIFO:=(others => (others=>'0'));

begin

range1<='0';
sgl<='1';
A2<='0';
cs<=xcs;
A1<='0';
A0<='0';
sclk<=xsclk;

process(clk)
begin
if rising_edge(clk) then

if count2=30 then
if start=1 then
avgA(0)<=xoutA;
elsif start=2 then
avgA(1)<=xoutA;
else
avgA(0)<=avgA(1);
end if;
elsif count2=31 then
avgA(1)<=xoutA;
end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
if count2=34 then
sumA<="0000000000000";

elsif count2=32 then
for i in 0 to 1 loop
sumA<= sumA + avgA(i);
end loop;
end if;
end if;
end process;


process(clk)
begin
if rising_edge(clk) then
if count2=33 then
favg_A<=conv_integer(sumA)/2;
end if;
end if;
end process;

process(clk)--
begin--
if rising_edge(clk) then--
if count2=34 then
if start<3 then
output<=conv_std_logic_vector(xoutA,12);
else
output<=conv_std_logic_vector(favg_A,12);
end if;--
end if;
end if;
end process;--

end Position_Estimator;

have you written a testbench to test this design before you compiled it?

TrickyDicky said:

have you written a testbench to test this design before you compiled it?

Click to expand...

Nope. I was trying directly with the synthesis. The other portion of the code (involving ADC interface) was found OK. Since there was some noise on ADC, it was decided to implement this filter.

try to put everything inside one process.
make sure count2 reaches the value "30" in the simulation. you better write a testbench code, even if it passes synthesis it may still have functionality bugs.