joder
Newbie level 6
Dear all,
The problem I met is I don't know how to do the ATPG at the chip level since I do the dft in the sub module.
Thus, the reported .spf is for the submodule instead of top module. But when doing ATPG, isn't it based on top level module to create patterns for the whole chip?
If I do the scan chain from the top, the test mode is enabled by trapping instead of using a single pin. What should I do?
Thx.
The problem I met is I don't know how to do the ATPG at the chip level since I do the dft in the sub module.
Thus, the reported .spf is for the submodule instead of top module. But when doing ATPG, isn't it based on top level module to create patterns for the whole chip?
If I do the scan chain from the top, the test mode is enabled by trapping instead of using a single pin. What should I do?
Thx.