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Problem in clock tree synthesis with Cadence Encounter

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kingslayer

kingslayer

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Dear all,

I am running in a problem while performing Clock Tree Synthesis using Cadence Encounter. I am using NanGate opencell 45nm standard-cell libraries. While editing the clock specification file, I got the following error, preceded by a warning:

**WARN: (ENCCK-994): Cell BUF_X1 has no timing arc. Check The timing libraries.
**ERROR: (ENCCK-724): Buffer BUF_X1 specified in the clock tree specification file is invalid.

I specify 'BUF_X1' cell in the clock configuration file as one of the buffers to use as follows

Buffer BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32

Which is the problem about that?

Thanks in advance
Cheers
 

This error means your libraries doesn't have timing information for the cell you specified in the clock tree specification file i.e BUF_X*. or forgot to read the timing library in which these cells are present. Open your library and check whether timing information for these cells is present or not.
 

If you have read the library and timing information is present, you should not get this error. Rerun and check whether error still exists.
 

I noticed that when I issue a 'checkDesign -timing' command before doing any floorplan, power plan and place step, I got something strange to me: the design uses 64 cells from the available library (and the names ensures me that the library is loaded correctly), however I am also informed that those 64 cells are missing with timing data. Also, I noticed that when I import the design using the 'File->Import Design' menu, I never specify the .lib file, but the only .lef one.

Can this be the problem? How to fix it in this case?

Thank you
Cheers
 

Open your .conf file. This file will be in your database directory. ADD below line in it and load the database again.
set rda_Input(ui_timelib,max) "Give your lib full path here"

Still I have one doubt, If you have not read timing library. How your prects optimization has happened?
 

Yes, by modifying manually the configuration file it works. I can also set max, min and "typical" libraries. Honestly, I don't know how I've been able to reach CTS without any prior compliant from the tool :-?

Thanks for your help

Cheers
 

Always check you log files for errors and warnings. Tool must have given your warning at placement and prects stage. Don't ignore warnings. If any warning is OK, you should know the reason behind it.
 

kingslayer,

I have a problem in clock tree synthesis and it seems that you have managed to solve this. I want to extract spice netlist of clock tree. I am using Nangate library and Encounter asks for cdb file of the library, such a thing does not exist and I should create this using oa2cdb tool. But it return some errors? Have you created cdb files? If so,
please let me know how.

Thanks in advance
 

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