achundur
Junior Member level 1
Hi all:
I am synthesizing a floating point ALU integrated with some other registers. After synthesis the netlist has a STD_ULOGIC type defined like this
-- define any necessary types
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";
subtype std_logic_2 is std_ulogic range 'U' to '-' ;
type std_logic_vector_2 is array (INTEGER range <>) of std_logic_2;
type mux_input_type is array (INTEGER range <>) of std_logic_vector_2 (48 downto 0);
But In my code there is no std_ulogic type.In synthesis script I am using compile_ultra command to compile and before writing netlist , I am using change_names command. Does anyone has any clue about thiis?
Thanks in advance
I am synthesizing a floating point ALU integrated with some other registers. After synthesis the netlist has a STD_ULOGIC type defined like this
-- define any necessary types
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";
subtype std_logic_2 is std_ulogic range 'U' to '-' ;
type std_logic_vector_2 is array (INTEGER range <>) of std_logic_2;
type mux_input_type is array (INTEGER range <>) of std_logic_vector_2 (48 downto 0);
But In my code there is no std_ulogic type.In synthesis script I am using compile_ultra command to compile and before writing netlist , I am using change_names command. Does anyone has any clue about thiis?
Thanks in advance