likewise
Newbie level 5
Hello,
in the example below, does the blocking assignment "y = a ^ b" also block the " q <= y" assignment until y is assigned?
module nbex1 (q, a, b, clk, rst_n);
output q;
input clk, rst_n;
input a, b;
reg q, y;
always @(a or b)
y = a ^ b;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else q <= y;
endmodule
Example 23 - Combinational and sequential logic separated into two always blocks
(from Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! -- Clifford E. Cummings)
Regards,
Leon.
in the example below, does the blocking assignment "y = a ^ b" also block the " q <= y" assignment until y is assigned?
module nbex1 (q, a, b, clk, rst_n);
output q;
input clk, rst_n;
input a, b;
reg q, y;
always @(a or b)
y = a ^ b;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else q <= y;
endmodule
Example 23 - Combinational and sequential logic separated into two always blocks
(from Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! -- Clifford E. Cummings)
Regards,
Leon.