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how to convert the layout into vhdl or verilog netlist or code?

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gautamraavi

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Hi

I am new to cadence virtuoso, trying to do some timing analysis on the SRAM.

I have built the SRAM cell layout using the cadence virtuoso .

I would like to know how can i convert the layout into VHDL or Verilog codes or the netlist?

And also would like to know which best tool to do timing analysis?
 

Refer to cadence tutorial. You can get the netlist file of your layout only if there is a schematic corresponding to your layout. Check with some import option in menu.

Also Xilinx ISE simulator is the best for doing timing analysis either by VHDL or Verilog code.

All the best.
 

Prashanth.vinnakota said:
You can get the netlist file of your layout only if there is a schematic corresponding to your layout.
Click to expand...

That's not quite correct, I think: The extraction tool (diva, assura, calibre) can extract a netlist from a layout -- it doesn't need a corresponding schematic for this. Only the LVS tool needs it.

If the layout has correctly labeled node and pin names, the extracted netlist will contain these.
 

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