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digital filter output quantisation

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91divine

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Guys i have designed a VHDL code for a 4th order digital filter.
It have 10bit input from a ADC and it should give 10bit output. But the simulator shows an error that output should be 20bit(double of input).
Can any one help me in quantisation of the 20bit output to 10bit for my further applications.
I have coded the filter in figure2 of **broken link removed**
 

What kind of error are you getting? For no loss of precision, if you have 10 bit input and 10 bit coefficients, you'll need 20 bit products. Then when you sum those four products, you'll need an additional 2 bits for the result. If you just want a 10 bit output, then you need to perform some rounding.
 

There are several methods for rounding. For the sake of discussion, assume you want to round an unsigned 20 bit number to 10 bits. Here's the simplest approach:

1) Take the 10 most-significant bits
2) Look at the 11th most-significant bit-if it's 1, add one to your 10 MSBs, otherwise add zero.
3) Done

This gets a little more complicated if you're using signed numbers, but you get the idea.

Think of it in terms of decimal numbers, if that helps. To round a decimal number, if the fractional part is greater than .5, you round your integer part up 1, otherwise, you just leave the integer part alone.
 
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