Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have always written complete IF's, but I've been using Synplify recently and it generates warnings about redundant code when I do that in a lot of places. In the past I have run into problems with incomplete IFs generating unintended results, so I just keep doing it the way I have-it won't cause any problems, the tools will eliminate redundant logic and I don't have to worry about it.
However, be aware that you may generate unintended latches if you don't write complete IFs.
inside a clocked process, the if just connects to the clock enable connection on the register. so incomplete ifs are usually a necessity. in an asynchronous process, an incomplete if will build a latch, which is usually a bad thing.
It is always useful to look into the synthesis report and check for any warning for latch. If that latch is an unwanted one then it should be removed, otherwise it may crate mismatches in netlist vs rtl simulation.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
