Synchronous state machine- design of a poller machine

Hi all! i am new to VHDL and i was ask to write a program in VHDL to implement a 3-input sequential Poller. The Poller has three inputs representing three devices. A device request service by asserting its input. On every clock cycle, the polling machine checks the status of the three input devices and generates an output code that identifies the asserted input(device) to be serviced, the device with the highest priority is selected. Each input is assigned a fixed priority denoted by its subscript; 3 is the highest priority and 1 is the lowest priority. To prevent "starving" the lower devices, the same asserted input is never selected on two successive pollings unless there are no other asserted pins.



Can anybody help me with this?

so whats the problems you're having implementing it?

when the input is "111" , req3 will be selected. if the input is "111" again, req2 will be selected. But when its "111" for the third time, it go back to req3 instead of req1

ok - post the code you're having problems with - have you written a testbench for it too?

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Poller is
port(Clock, nreset : in std_logic;
Req : in std_logic_vector(3 downto 1) :="000";
Ack : out std_logic_vector(1 downto 0));

end Poller ;

architecture Behavior of Poller is
type states is (None, Req1, Req2, Req3);
signal state : states;
begin
moore : process (Clock, nreset)
begin
if nreset = '1' then
state <= None;

elsif (Clock'event and Clock='1') then

case state is
when None =>
if req(3) ='1' then
state <= Req3;
elsif req(2) ='1' then
state <= Req2;
elsif req(1) ='1' then
state <= Req1;
end if;

when Req1 =>
if req(3) ='1' then
state <= Req3;
elsif req(2) ='1' then
state <= Req2;
elsif req(1) ='1' then
state <=Req1;
end if;

when Req2 =>
if req(3) ='1' and req(2) ='0' and req(1) ='0' then
state <= Req3;
elsif req(3) ='1' and req(2) = '1' and req(1) ='0' then
state <= Req3;
elsif req(3) ='1' and req(2) ='0' and req(1) ='1' then
state <= Req3;
elsif req(3) ='0' and req(2) ='1' and req(1) ='0' then
state <= Req2;
elsif req(3) = '0' and req(2)='0' and req(1) ='1' then
state <= Req1;
end if;

when Req3 =>
if req(3) = '1' and req(2) ='0' and req(1) ='0' then
state <= Req3;
elsif req(3) ='1' and req(2) ='1' and req(1) ='0' then
state <= Req2;
elsif req(3)='1' and req(2) ='0' and req(1) ='1' then
state <= Req1;
elsif req(3) ='0' and req(2) ='1' and req(1) ='1' then
state <= Req2;
elsif req(3) ='0' and req(2)='1' and req(1) ='0' then
state <= Req2;
elsif req(3) ='0' and req(2) ='0' and req(1) ='1' then
state <= Req1;
end if;




end case;
end if;
end process;

Ack <= "00" when (state=None) else
"01" when (state=Req1) else
"10" when (state=Req2) else
"11";


end Behavior;

and whats the problem?

Be honest: is this a college assignment you want us to do for you?

ps: never think of vhdl as a program, it's not