Hi everyone.

I have a college work where I have to use a VHDL file that was given to me. But whoever made this file used std_logic_arith. So I went and converted it to numeric_std. So far so good, but now I had to add some content, and it's failing to work.

I have to use the SLL operator with std_logic_vector. I know it's not ideal, but it would be FAR too difficult to change all of the std_logic_vector. Searching a little I invented the following way:

Code:
opout <= to_stdlogicvector(to_bitvector(op2) sll to_integer(unsigned(op1)));
I used Xilinx ISE to check the syntax and it's ok. But it did not performed as expected on ModelSim, where I'm testing a whole single-cycle 32 bits MIPS processor. Then I made a very simple architecture and test bench to test the operation on ISE, and the result was zero. But it also gave a warning:
Code:
Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
How can I make SLL work here?