omar-malek
Member level 5
Hi to all,
i develop a system using VHDL language.
so i have to module one work with speed clock and generate signal enable for one cycle speed clock, this signal wired to other enable signal
that work with slow clock, so the problem the enable signal of second system (work with slow clock) haven't the sufficient time to activate a process with slow clock you can see the picture for more detail.
so any one give me an idea for this problem.
thank you in advance.
i develop a system using VHDL language.
so i have to module one work with speed clock and generate signal enable for one cycle speed clock, this signal wired to other enable signal
that work with slow clock, so the problem the enable signal of second system (work with slow clock) haven't the sufficient time to activate a process with slow clock you can see the picture for more detail.
so any one give me an idea for this problem.
thank you in advance.