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Problem with port defined as inout in a module (Verilog)

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lokeyh

lokeyh

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Question on Verilog

Hi all,

I am new to verilog. I have a problem.

I have a port on a module that is defined as inout. Sometimes, I need to drive it with a signal and sometimes, the port need to drive a signal. VCS gives errors when I drive the port with register. What should I write in the testbench to avoid that error.

Thanks.
 

Re: Question on Verilog

assign ur register to a wire and connect this port to a wire ... but make sure u r driving Z when u don't want to drive any value!!!!
 

Question on Verilog

a module's output must be connected to a wire,iout is also.
 

Question on Verilog

For inout signal both inside the module as well as during instantiation of that module it should b e connected/driven by a wire.
 

Question on Verilog

module XXX(
...
s_inout,
...
);
...
inout s_inout;
...

wire s_inout;

assign s_inout = s_out_oe?r_inout:z;

...

Good Luck
 

Re: Question on Verilog

you should write your code as follow:

////////////////////////////////////////////////

inout bir_signal;

wire oe; // add this control signal
wire signal_input;
reg reg_out;

assign bir_signal = oe? reg_out : 1'b1;
assign signal_input = bir_signal;

/////////////////////////////////////////////////

one must think about hardware implementation when he(or she) is writing code;






lokeyh said:
Hi all,

I am new to verilog. I have a problem.

I have a port on a module that is defined as inout. Sometimes, I need to drive it with a signal and sometimes, the port need to drive a signal. VCS gives errors when I drive the port with register. What should I write in the testbench to avoid that error.

Thanks.
Click to expand...
 

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