resistor mismatch of large distance in 130nm process

hi,
two resistor is the same size, but the distance between them is about 200um, does the mismatch exceed 1%?
thanks.

For matching any devices, you have to place them as close as possible, use interdigitation technique and add dummies at the end.. Run montecarlo/dcmatch sims to find out how it matches..

thank you ,
i know the layout rule for resistor match. i just want know how much mismatch will be caused, when the distance between resistors is about 200um.

huangjw said:

i just want know how much mismatch will be caused, when the distance between resistors is about 200um.

Click to expand...

For this you need the distance dependent mismatch parameter A_dist [%] for your process and this special resistor from your fab/foundry.
Then you can calculate/estimate their possible mismatch: σ(ΔR/R)=A_dist*dist/√(W*L)

hi, erikl,
our process has no the parameter Adist, so can you show me your process's parameter Adist, i could reference it.
thanks

Nor do I have A_dist values for a 130nm process, sorry! Anyway, they aren't necessarily comparable between different foundries, and they even may differ for different resistor materials.

Just to give you an impression of the order of magnitude: For a 180nm process, we were given an estimate value of A_dist = 1% for low-ohmic (salicided) poly resistors, and about ¾ of this value for high-ohmic (non-salicided) poly resistors.

Mismatch values -- to a first order approximation -- scale linearly with process size.

hi, erikl,
your parameter is so large that i can't believe it. if two resistor's distance is 200um, and the w*l is 10um*10um, the mismatch will be 20%. I know the diference of square resistance for all process corner will not exceed 15%.

huangjw said:

... your parameter is so large that i can't believe it.

Click to expand...

Of course you don't need to believe it! ;-) :razz:

huangjw said:

if two resistor's distance is 200um, and the w*l is 10um*10um, the mismatch will be 20%. I know the diference of square resistance for all process corner will not exceed 15%.

Click to expand...

You forgot process scaling -- then 14% instead of 20%. Without salicide effect: 11% . Less than your corner variations -- is this 15% value variation or mismatch? You know (uncorrelated) mismatch adds quadratically.

With such a "huge" distance between resistors which should match, wafer-wide process variation may easily outnumber local (up to ≈100*process size) and corner mismatch. But of course this depends on process management and lateral control quality of all its influencing steps (lithography, poly thickness and doping, saliciding). I think obliging data you can get only from your fab/foundry -- if ever. :sad:

If you need good matching and want to get rid of large scale variations, you better put them as close as possible -- common centroid -- even interlace them.
__
PS: May be they gave us such bad A_dist values to enforce keeping together devices which should match? Perhaps w-wc values in order to reject wafer scale accuracy responsibility?