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simulation completed, what next...?

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Jaffry

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Dear all,

I am relatively new in FPGA practical design, earlier I had expereince of simulation designs for verilog and VHDL
models.

This time I am working on a practical project. For that I have completed my simulation phase and the results are good to be implemented.

Now the implementation phase have arrived and I need guidance in this regard, I have done homework regarding my next steps. but any help would be beneficial and would increase my speed since I have to complete this (and finished and delivered) within 1 1/2 month from now...

My next steps should be (Please provide with a good thorough link or materail as well if can)

1) Static Timing Analysis (Dynamic Timinig analysis- if required)
This is the most time consuming phase I think will be for me. Since I could not understand what clock frequency is best for my design. I have read about timing constraints, but how to find the parameters using reports is difficult. I can also share details what difficulties I find....

2) Place and Route : This Xilinx ISE will do itself based on .UCF file and STA

3) download into fpga: using iMpact. I have idea of this as I have done this several time with small projects like counter, d flipflops etc.


Note : I am using xilinx V6 Fpga board + Xilinx ISE software and Language is Verilog


Best Regards,
Jaffry
 

1). Usually, your clocks are set at the design phase. Interfaces may need to run at a certain speed, or you require a specific data rate - that will usually dictate your clock speed. So this will mean specifying the clock and seeing if the design will actually work at the specified clock rate. You can usually do this as part of 2), as you will need to synthesise the code anyway to see if it synthesises to what you want, if not, or it doesnt meet timing, you have to make changes to the code and go back to the simulation phase to see if it still works.

3). You need to make sure you have something to drive the FPGA - some input source, but this bit can take just as long as 1 and 2, but with good simulation it should minimuse any problems.
 
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    Jaffry

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Thank you sir for your reply

How can I find the maximum period between any two registers in my desing (critical path) using the reports...?
Also through out my design I have used the same clock for all the gates and flops, registers...i.e. every thing is in single clock domain (as I designed) is it good (practically possible) i.e. concerned about fan outs etc. since I dont knwo about distributing the clock using clocking wizard.

Also I have seen the XILINX REL for clocking resources and studied the guide as well, but implementation is not clear...!
Any useful material or suggestion...?

I know it might seem little messed up but learning on your own from scratch is a fun as well as time consuming which I do not have much...

Bests
Jaffry
 

A single clock domain is usually desired. Crossing clock domains causes all sorts of headaches.
As a first step, I suggest synthesising the design to make sure it actually synthesises - as a beginner you have have fallen into some unsynthesisable pitfalls some beginners experience. After this you can look at the timing reports. Im more an altera person, and they have a nice FMax report from TimeQuest - Im sure Xilinx do something similar.
 
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    Jaffry

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It might be also a good idea to consider ChipScope (to insert logic analyzer, bus analyzer, and virtual I/O low-profile software cores directly into your design) for testing and debugging purposes.

-Vonn
 

Thank you all for your reply.

Yes I synthesized the design. It is synthesized (of-course I had to fix some problems :)) Any ways. So I am getting some warnings (some of which are related to IP cores I guess, i.e. Divider core )

So should I ignore these warnings.

Also I tried one more thing...
A single clock domain is usually desired. Crossing clock domains causes all sorts of headaches.
Got it, but qeustion regarding clock
So I used clocking wizard in a test proejct and was able to generate clock as well (from 66MHz crystal converted to 10MHz crystal and checked the LSB of 23 bit counter...:) )
Now I have this question...
On what basis should I select BUFG, BUFH, BUFGE, no buffer etc...

Also how should what should I put in place of Input jitter value since I don't know what jitter the oscillator clock or external clock is going to give ...?

@Vonn..Sir I tried Chipscope as well earlier for simulation but had problems, I guess I did not instantiated cores and expected unexpected :) , but will definitely try it again. Thanks
 
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