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Writing verilog code for 3 signals with their delays

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dmx-512

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Hi, I need a help in writing a verilog code for some signals like CLK, CKE, and RESET with their delays.
I have written the code according to my knowledge but there are some conflictions in that.
Iam here attatching the related document along with my code please check it out and suggest me. thank you.



Code: 
`timescale 1ns / 1ps

module DDR3_Rst(
                  clk,
              Reset,
	cke
    );
	 
	 input clk;
	 output Reset;
	 output cke;
	 
	 reg Reset_i;
	 reg cke_i;
	 
 always@(clk)
 begin

 if(clk)
 begin
#0 Reset_i <= 1'b0;
#44 cke_i <= 1'b1;
 end
 
 else
 
 if(!clk)
 begin
#200655 Reset_i <= 1'b1;
  #189985 cke_i <= 1'b0;
#310162 cke_i <= 1'b1;
 end
 
 end
 

 assign Reset = Reset_i;
 assign cke = cke_i;
 

endmodule
 

Dear
Well I cannot get the clear idea what you are trying to do

But for sure the inclusion of # for timing it will not generate any synthesized result for you.
You have to add some timers and counters that will do the timing for you
Like you want to hold reset low for 200us. What is the clock speed of your clock

If let us assume your clock frequency for the design is 100 kHz...i.e. 10us.
Then you need 20 delays for reset to remain low. You can include timer which will count every clock
after the RESET# gets low and as soon as it gets 20 you signal RESET# to be high...

For that case I guess you also need some Master_reset. Other people can help correcting this idea of mine
What I think (only for reset) it will be like that

Code: 
always@(posedge clk)
if(Master_reset) begin RESET <= 1'b1; timer<=0;end 
else
 if(!RESET) if(timer<20) timer <= timer+1'b1;
                   else timer <= 0; RESET <=1'b1;
 else.... // If not(!RESET)
  ...

similarly you can look into for the other signals
 
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    FvM

    FvM

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    dmx-512

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CLK is 500 MHz.
the steps below follows the code

• Until the power supplies are stable, maintain RESET# LOW to ensure the outputs
remain disabled (High-Z). After the power is stable, RESET# must be LOW for at least
200μs to begin the initialization process.
• CKE must be LOW 10ns prior to RESET# transitioning HIGH.
• After RESET# transitions HIGH, wait 500μs with CKE LOW.
• After the CKE LOW time, CKE may be brought synchronously HIGH while only NOP
or DES commands are issued. The clock must be present and valid for at least 10ns
(and a minimum of 5 clocks) . After CKE is registered HIGH, it must be
continuously registered HIGH until the full initialization process is complete

So can u please modify my code and say me.
 
Last edited:

Are you writing a testbench or designing a synthesizable memory controller? in the latter case, you can't use "#" delay statements.
 

writing synthesizable code, so without using # how can i write this, please help me how can i modify my code
 

In this as iam using a stable clock of 500 MHz then how can i count the cycles as it is a stable clk
 

dmx-512 said:
In this as iam using a stable clock of 500 MHz then how can i count the cycles as it is a stable clk
Click to expand...

I severly doubt you are using a 500MHz clock on an FPGA. 50Mhz is more realistic.
 

ya iam using 500 Mhz clock itself
 

With fast FPGAs and e.g. DDR3 RAM, the memory clock may be as high as 500 MHz. The core operating frequency will be however lower in most parts, the design needs to work in multiple clock domains.
 

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