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Initialize Lookup Table Verilog

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carleethian

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I want to create a lookup table inside an array. The code below won't compile, can someone please let me know what I'm doing wrong? Does the for loop need to be in the always block? What I really want is for the compiler to do all the math and load the values into memory...

Code:
localparam	BIT_WIDTH = 8;
localparam	NUM_STATES = 255;

reg	[BIT_WIDTH-1:0]	State_Array [0:NUM_STATES-1];

for (i=0; i < NUM_STATES; i = i + 1)
  begin
    State_Array[i] = 1000000 * i / (i+1);
  end

always @ (....)

Does anyone know how to do this or maybe know of a better way?
 

If you can use SystemVerilog, you can have an initialization call a function that returns the filled out array.

Code:
typedef bit [BIT_WIDTH-1:0] LUT_t [NUM_STATES];

LUT_t State_Array = LUT_init;

function LUT_t LUT_init();
  foreach (LUT_init[i]) LUT_init[i] = 1000000 * i / (i+1);
endfunction
 
So that won't create a divider in hardware? I'm trying to avoid the divider and do all of my multiplies & divides before compilation.
 

All of the equations/functions used to create constant expressions do not generate any hardware. The compiler resolves them at elaboration before synthesis begins.
 
Hi Dave, so is there not a way to get this to work in Verilog? The only way I've initialized memory is in reset, am I correct that if I put something like that for loop inside my reset statement inside my always block, that because it's creating constant expressions it won't synthesize into hardware?
 

A for loop will be unrolled by a synthesis tool as long as the number of iterations of the loop can be determined statically at compile time. A synthesis tool will do this regardless of it being a Verilog generate for-loop or a procedural for-loop statement. The loop variable then becomes a constant, and any expression based solely on constants does not turn into hardware.
 

Hi Dave,

Wont it be better to use this for-loop in test-bench and load the calculated values into RTL during reset? AM nt sure. Pl guide.
 

you want something like an inital block. eg:
Code:
initial begin
  //code
end

you can also use $readmemb, or $readmemh, or $readmem to initialize the ROM from a file. Both Xilinx and Altera support this.
 

I'm under the impression that a initial block won't synthesize in Verilog...

What I've done is that I'm using a for loop to calculate the values for the lookup table during reset. Just like Dave said, the compiler seems to run through the for loop and store all the values in memory. Thus, the math operations won't synthesize into hardware. This is apparent in my Total LE count as it stays low with or without the calculations.

Or at least I think it's doing all the calculations... The array isn't showing up in my simulation so I'm not completely sure it's there.
 

RAM/ROM initialization code inside initial block will be honored by the synthesis tool. Check this post Memory Initialization Methods for some examples.

I'm under the impression that a initial block won't synthesize in Verilog...

What I've done is that I'm using a for loop to calculate the values for the lookup table during reset. Just like Dave said, the compiler seems to run through the for loop and store all the values in memory. Thus, the math operations won't synthesize into hardware. This is apparent in my Total LE count as it stays low with or without the calculations.

Or at least I think it's doing all the calculations... The array isn't showing up in my simulation so I'm not completely sure it's there.
 

Hi Jim,

I went through your blog now and would like to appreciate the efforts you have taken to maintain it. Reagarding memory instantiation you have spoken wrt FPGA design. Can u comment on the ASIC counterpart?
 

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