sigma delta fractional divider

hi
i want to do sigma delta fractional divider, i an not getting suitable architectures for that.
Could you give any suggestion or do u have any architecture for that tell me please.

what have you done so far?

i have done programmable divider, i have this reference paper,,
IMPLEMENTATION OF A PROGRAMMABLE HIGH SPEED DIVIDER FOR
A 2.4 GHZ CMOS INTEGER-N FREQUENCY SYNTHESIZER
But in this divider only dividing fixed ratio, But i want 2 different dividing ratios, i mean when sigma delta output 0 it will divide by N ratio and when sigma delta output 1 it will divide by N+1 ratio.
Could you please suggest me any other architecture regarding this.

Thank you.

post up some code and we'll see where we can go

`include "constants.vams"
`include "disciplines.vams"

module digRfPllTopDivider(DOUT, DIN, control);

output DOUT; voltage DOUT; // output
input DIN; voltage DIN; // input (edge triggered)
input control ;
voltage control;
parameter real vh=+1; // output voltage in high state
parameter real vl=0; // output voltage in low state
parameter real vth=(vh+vl)/2; // threshold voltage at input
// parameter integer ratio=20 from [2:inf); // divide ratio
parameter integer dir=1 from [-1:1] exclude 0;
// dir=1 for positive edge trigger
// dir=-1 for negative edge trigger
parameter real tt=1p from (0:inf); // transition time of output signal
parameter real td=0 from [0:inf); // average delay from input to output
integer count, n , ratio, x;
analog begin
@(cross(V(DIN) - vth, dir))
begin
x=V(control);
if (x ==0) begin
ratio=19 ;
end else begin
ratio=20 ;
end
count = count + 1; // count input transitions
if (count >= ratio)
count = 0;
n = (2*count >= ratio);
end
V(DOUT) <+ transition(n ? vh : vl, td, tt);
end

This is may code of divider, here Vcontrol is the sigma delta output, if its 0 divide by 19, if its 1 divide by 20 like that it will act.
i want to it in schematic level.
please suggest me suitable architecture for this.

Thank you.

Hi
I have posted code yesterday.
Could you give any suggested architecture for that.