Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to fix the "setup and hold time " in DC flows.

Status
Not open for further replies.
G

googler123

Junior Member level 1
Joined
Dec 8, 2011
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,400
Hi All,


How to fix the "setup and hold time violations" in DC flows.

And How to optimize the designs using the DC ?


BR
Thanks,
 

during the synthesis phase you only fix the setup time. Hold time is only done after clock tree in PnR tool.
 

Absloutely During Synthesis setuptime is fixed and hold can be fixed only after CTS(Clock Tree Synthesis) and if the setup time is met we proceed to further steps else if the setup time is not met we come back and do the logic optimization by adding buffers and resizing of cells....,

Hope this can help you....,

With Regards,
D.Raviteja.
 

rca said:
during the synthesis phase you only fix the setup time. Hold time is only done after clock tree in PnR tool.
Click to expand...

Thanks,

But Could you give me more information? How to fix the setup time violations in DC Synthesis ?Maybe ,wish you share a handbook or a example .

I am a fledgling...

BR
Thanks.

---------- Post added at 20:37 ---------- Previous post was at 20:35 ----------
ravipandu46338@gmail.com said:
Absloutely During Synthesis setuptime is fixed and hold can be fixed only after CTS(Clock Tree Synthesis) and if the setup time is met we proceed to further steps else if the setup time is not met we come back and do the logic optimization by adding buffers and resizing of cells....,

Hope this can help you....,

With Regards,
D.Raviteja.
Click to expand...

Thanks,

But Could you give me more information? How to fix the setup time violations in DC Synthesis ?Maybe ,wish you share a handbook or a example .

I am a fledgling...

BR
Thanks.
 

you need to analyze the worst path, then there is two cases:
1- true path, need to check with the designer if this path could be optimized by design or check if the appropriate logic been used by the synthesis tool.
2- false path, add a set_false_path.
 

hai
you can refer this manual for Design-Compiler and clarify your doughts


thank you
 

Attachments

  • dctut.pdf
    1.2 MB · Views: 257

Re: How to fix the "setup and hold time " in DC flows.

Hello sir ,

why Hold time is fixed after CTS and setup in preCTS phase ? am luking for this answer since long time now. after CTS buffers are added , so how does this fix hold time. pls correct me !!!!
rca said:
during the synthesis phase you only fix the setup time. Hold time is only done after clock tree in PnR tool.
Click to expand...

- - - Updated - - -

Hello sir ,

why Hold time is fixed after CTS and setup in preCTS phase ? am luking for this answer since long time now. after CTS buffers are added , so how does this fix hold time. pls correct me !!!!
rca said:
during the synthesis phase you only fix the setup time. Hold time is only done after clock tree in PnR tool.
Click to expand...
 

Hi

During preCTS the clock is considered to be am ideal clock and hence the hold violation that occurs due to skew cannot happen(as it is ideal). Hence, we go only for setup check during preCTS stage. Once CTS is done, ideal clocks are replaced by real clocks and hence skew appear which may lead to hold violations. To cure hold violation, we may have to increase the datapath delay(without causing setup violation) or reduce skew.
 
This issue has been discussed many times my friend. please spare some time to look at the forum. cheers
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top