fahadislam2006
Member level 2
Hi,
To see the architectural difference of blocking and non-blocking statement, I implemented a simple code of a sequential circuit in verilog with both blocking a non-blocking,
always (posedge clk)
c <= a+c;
then I synthesized (using ISE) and viewed both RTL and Technology schematic. In both cases, I am unable to find any difference.
I know the basic concept of blocking non-blocking that the later not block the coming statements and the calculations of right hand side are just assigned on clock edge, but my question is about architectural difference
To see the architectural difference of blocking and non-blocking statement, I implemented a simple code of a sequential circuit in verilog with both blocking a non-blocking,
always (posedge clk)
c <= a+c;
then I synthesized (using ISE) and viewed both RTL and Technology schematic. In both cases, I am unable to find any difference.
I know the basic concept of blocking non-blocking that the later not block the coming statements and the calculations of right hand side are just assigned on clock edge, but my question is about architectural difference