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FPGA architecture related question (blocking and non blocking difference)

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fahadislam2006

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Hi,
To see the architectural difference of blocking and non-blocking statement, I implemented a simple code of a sequential circuit in verilog with both blocking a non-blocking,

always (posedge clk)
c <= a+c;


then I synthesized (using ISE) and viewed both RTL and Technology schematic. In both cases, I am unable to find any difference.

I know the basic concept of blocking non-blocking that the later not block the coming statements and the calculations of right hand side are just assigned on clock edge, but my question is about architectural difference
 

in some cases it is just a simulation issue. in others, it matters:

Code: 
always @ (posedge clk) begin
  x = y;
  if (x < 0) begin
    x = -x;
  end
  dout <= x;
end
in the above, the blocking assignements mean x will not infer a register. note that x cannot generally be used outside of the always block becasue the always block is clocked. this isn't enforced by the simulator/synthesizer. If x is used outside of the process, the evaluation order of the processes will become important for simulation.
 

    V

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It's always the context that matters. A single blocking or non-blocking statement has no "architectural" meaning in the context of your initial example. In clock edge sensitive always blocks, the only reasonable application of blocking statements is for intermediate results, as in the example shown by permute. If x isn't used outside the block, the generated RTL looks like
Code: 
always @ (posedge clk) begin
  if (y < 0)
    dout <= -y;
  else 
    dout <= y;
end
 

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