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the full and empty of FIFO

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sun_ray

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Please answer the followings:

1. Is it that an asynchronous FIFO may not have the full and empty signal also?

1. Is it that a synchronous FIFO may not have the full and empty signal also?

Regards
 

I saw that paper earlier. It does not answer the questions directly . I want the above two questioned to be answered.
 

sun_ray said:
Please answer the followings:

1. Is it that an asynchronous FIFO may not have the full and empty signal also?
2. Is it that a synchronous FIFO may not have the full and empty signal also?
Click to expand...
FIFO is "first in, first out" block design used in many field.
the signal "full" and "empty" is to indicate the user whether the data is available.
If the storage of FIFO is known (designed by user), for example, never full or empty, the answer is yes.

However, for normal usage, it's assumed that the storage mode is unsure.
How many data will be arrived and how many data will be fetched in specific time is unknown.
This is why we use vendor FIFO instead of shift register or other storage. For general case, the answer is no.
 

YuLongHuang said:
If the storage of FIFO is known (designed by user), for example, never full or empty, the answer is yes.
Click to expand...

What do you mean by storage here? Is it the depth of FIFO? Can you please explain your above quite as it was not understod. What do you mean by 'never full or empty'?

Regards

---------- Post added at 02:55 ---------- Previous post was at 02:54 ----------
YuLongHuang said:
If the storage of FIFO is known (designed by user), for example, never full or empty, the answer is yes.
Click to expand...

What do you mean by storage here? Is it the depth of FIFO? Can you please explain your above quite as it was not understood. What do you mean by 'never full or empty'?

Regards
 

For example :
You are decoding a block coding such as RS, and 255 symbols are stored temporarily.
After complicated decoding procedure, you will fetch the stored symbols for correcting after some period of clock.
Since the mechanism is ensured, you will only stored the received symbols in the FIFO once the output answer is generated.

Because of that, the FIFO is never full and thus it's unnecessary to check out the status of FIFO.
In the other words, since the designer always knows the status of FIFO, it's redundant to check out the flag again.
 

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