[SOLVED] Computer Architecute lite Single cycle MIPS design problem

----------------------ENTITY-----------------------------
entity test_env is
	
    Port ( clk : in  STD_LOGIC;
           btn : in  STD_LOGIC_VECTOR (3 downto 0);
           sw : in  STD_LOGIC_VECTOR (6 downto 0);
           led : out  STD_LOGIC_VECTOR (7 downto 0);
           an : out  STD_LOGIC_VECTOR (3 downto 0);
           cat : out  STD_LOGIC_VECTOR (6 downto 0);
           dp : out  STD_LOGIC);
end test_env;
---------------------END---------------------------------


architecture Behavioral of test_env is
	
	----------------------MPG component-------------------
	component mpg is
   Port ( clk : in  STD_LOGIC;
           btn : in  STD_LOGIC_VECTOR (3 downto 0);
           step : out  STD_LOGIC_VECTOR (3 downto 0));
	end component;
	-------------------------END--------------------------
	
	----------------------SSD component-------------------
	component ssd is
    Port ( 	d1 : in std_logic_vector(3 downto 0);
				d2 : in std_logic_vector(3 downto 0);
				d3 : in std_logic_vector(3 downto 0);
				d4 : in std_logic_vector(3 downto 0);
            anod : out  STD_LOGIC_VECTOR (3 downto 0);
            catod : out  STD_LOGIC_VECTOR (6 downto 0);
            clk : in  STD_LOGIC);
	end component;
	-------------------------END--------------------------
	
	
	-------------------REGISTER component-----------------
	component reg_file is 
	port ( 	clk : in std_logic; 
				ra1 : in std_logic_vector (3 downto 0); 
				ra2 : in std_logic_vector (3 downto 0); 
				wa : in std_logic_vector (3 downto 0); 
				wd : in std_logic_vector (7 downto 0); 
				wen : in std_logic; 
				rd1 : out std_logic_vector (7 downto 0); 
				rd2 : out std_logic_vector (7 downto 0)); 
	end component;
	-------------------------END--------------------------
	
	
	-------------------ALU component----------------------	
	component cascade_alu is
	generic ( 
		width : natural range 4 to 16 := 8 
		);
		port( 
				a 			: in std_logic_vector(width - 1 downto 0);
				b 			: in std_logic_vector(width - 1 downto 0);
				c_ainv 	: in std_logic; 
				c_binv 	: in std_logic; 
				c_aluop	: in std_logic_vector(3 downto 0); 
				c_ovf		: out std_logic;
				c_zero 	: out std_logic;
				res		: out std_logic_vector(width - 1 downto 0)
		); 
	end component;
	-------------------------END--------------------------
	
	-----------------------SIGNALS------------------------
	signal rcnt 	: std_logic_vector(7 downto 0);

	
	
	type mem is array (0 to 2**8-1) of std_logic_vector (15 downto 0); 
	type ram_type is array (0 to 2**8-1) of std_logic_vector (7 downto 0);
	
	
	signal pc_count: std_logic_vector(7 downto 0);
	
	signal step 	: std_logic_vector(3 downto 0);
	signal step_d 	: std_logic_vector(3 downto 0);
		

	signal op 			:  std_logic_vector (3 downto 0); 
	signal ra1 			:  std_logic_vector (3 downto 0); 
	signal ra2 			:  std_logic_vector (3 downto 0); 
	signal wa 			:  std_logic_vector (3 downto 0); 
	signal wd 			:  std_logic_vector (7 downto 0); 
	signal rd1 			:  std_logic_vector (7 downto 0); 
	signal rd2 			:  std_logic_vector (7 downto 0); 
	signal imm			:  std_logic_vector (7 downto 0); 
	
	signal disp 		: std_logic_vector(15 downto 0);
	signal rom_d 		: std_logic_vector(15 downto 0);

	
	-- control signals
	signal regWrite	: std_logic;
	signal regWritei	: std_logic;
	--control signals for ALU--
		--NOTE: caryy in nu trebuie, e aceeasi cu b_inv--
	signal a_inv,b_inv,ovf,zero:std_logic;
	signal res:std_logic_vector(7 downto 0);
	
	--ALU src--
	signal alu_src:std_logic;
	signal data2:std_logic_vector(7 downto 0);
	
	--RegDst--
	signal RegDst: std_logic;
	
	attribute equivalent_register_removal: string;
	
	attribute equivalent_register_removal of rom_d : signal is "no";
	
	
	-- DMEM --
	signal memWrite:std_logic;
	signal temp:std_logic_vector(7 downto 0);
	signal DMEM : ram_type:=(	x"44",
										x"44",
										x"44",
										x"44",
										x"44",
										x"44",
										x"44",
										x"44",
										others => x"11"
									);
	signal we:std_logic;
	attribute equivalent_register_removal of temp : signal is "no";
	
	signal ROM 		: mem := (
		x"0005",
		x"0019",
		x"0024",
		x"0035",
		x"0049",
		x"0054",
		x"0005",
		x"0015",
		x"0025",
		x"0035",
		x"0046",
		x"0056",
		x"0036",
		x"0046",
		x"0056",
		x"0066",
		x"0076",
		x"0086",
		x"0096",
		x"0006",
		x"0017",
		others => x"0000"
	);


begin
	
	mpg1: mpg 
	Port map ( 
		clk => clk, 
		btn => btn, 
		step => step 
		);
		
	ssd1: ssd
	Port map ( 
		d1 => disp(15 downto 12),
		d2 => disp(11 downto 8),
		d3 => disp (7 downto 4),
		d4 => disp (3 downto 0),
      anod => an,
      catod => cat,
      clk =>clk
		);
		
	ALU: cascade_alu
	Port map (
				a 			=>rd1,
				b 			=>data2,	--rd2 sau imm
				c_ainv 	=>a_inv,
				c_binv 	=>b_inv,
				c_aluop	=>op,
				c_ovf		=>ovf,
				c_zero 	=>zero,
				res		=>res
				);
				
	process(clk)
	begin
		if rising_edge(clk) then
			step_d <= step;
		end if;
	end process;
	
	-- program counter
	process(clk)
	begin
		if rising_edge(clk) then
			if step_d(1) = '1' then
				pc_count <= pc_count + 1;
			end if;
		end if;
	end process;
	
		-- temp counter for DMEM
	process(clk)
	begin
		if rising_edge(clk) then
			if (step_d(2) or step_d(3)) = '1' then
				rcnt <= rcnt + 1;
			end if;
		end if;
	end process;
	
	-- rom
		rom_d <= ROM(conv_integer(pc_count));
		
	--DMEM--
	process (clk,rcnt,rd2,we,memWrite)
		begin
			if rising_edge(clk) then
				if we ='1' then
						if memWrite = '1' then 
							DMEM(conv_integer(res)) <= rd2; 
						else
							temp<= DMEM( conv_integer(rcnt));
							end if;
				end if;
			end if;
	end process;
	
	
	led <= rcnt;

	
	-- instruction decode
	op 	<= rom_d(15 downto 12);
	ra1 	<= rom_d(11 downto 8);
	ra2 	<= rom_d(7 downto 4);
	imm 	<= "0000" & rom_d(3 downto 0);
	
	-- RegDst MUX --
	process(rom_d(3 downto 0), imm,RegDst,wa,ra2,pc_count)
		begin
			if RegDst ='1' then
				wa<=rom_d(3 downto 0);
			else
				wa<=ra2;
			end if;
	end process;
	
	-- reg file
	reg_file1: reg_file
	Port map (
		clk => clk, 
		ra1 => ra1, 
		ra2 => ra2, 
		wa => wa, 
		wd => wd, 
		wen => regWrite,
		rd1 => rd1, 
		rd2 => rd2
	);
	
	
	-- control unit --
	process(op,pc_count)
	begin
		case op is 
			-- add
			when "0000" 	=> regWritei <= '0';
			-- addi
			when "0001" 	=> regWritei <= '0';
			when others 	=> regWritei <= '0';
		end case;
	end process;
	
	--Alu src MUX--
	process(alu_src,imm,rd2,pc_count)
	begin
		if alu_src ='1' then
				data2<=imm;
		elsif alu_src = '0' then
				data2<=rd2;
		end if;
	end process;

	process(clk)
	begin	
		if rising_edge(clk) then
			if step(1) = '1' then
				regWrite <= regWritei;
			else
				regWrite <= '0';
			end if;
		end if;
	end process;
	
	
	-- To BCD --
	process(sw,rom_d,rd1,rd2,imm,wd,pc_count,temp,res)
	begin
		case sw(1 downto 0) is
			when "00"	=> disp <= rom_d;
			when "01"	=> disp <= rd1 & rd2;
			when "10"	=> disp <= "00000000"&res;--"0000"&ra1 &"0000"&ra2;
			when others => disp <= "00000000"&temp;--x"00" & wd;
		end case;
	end process;
	
	dp <= zero;
	a_inv<=sw(2);
	alu_src<=sw(3);
	RegDst<=sw(4);
	memWrite<=sw(5);
	we<=sw(6);
	b_inv<=step_d(0);
	
	
	
end Behavioral;

--DMEM--
	process (clk,rcnt,rd2,we,memWrite)
		begin
			if rising_edge(clk) then
				if we ='1' then
						if memWrite = '1' then 
							DMEM(conv_integer(res)) <= rd2; 
						else
							temp<= DMEM( conv_integer(rcnt));
							end if;
				end if;
			end if;
	end process;