How to handle different clock domains + bist clock logic in scan and atpg?

I have two clocks in my design one at running at 80Mhz and another at 500Mhz.
The scope is we are using single test clock for the design. So when I stritch scan (DFTA) I am putting one mux at the output of clock_gen (clk generator module) to bypass the internal generated clock. Now all the scan FFs are connected to TCK while scan_mode=1 .

i) Will it create timing during STA(scan_mode shift)?

ii) How should I handle the at-speed atpg for these two domains?(design has internal PLL).

iii)

Can you please anyone help on this?

Hi , can any one please clarify on this?

kothandapani said:

i) Will it create timing during STA(scan_mode shift)?

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Not sure what you meant by " Will it create timing". Did you mean timing violation?

For scan chains, there is shift mode and capture mode. One way to configure your design for scan chain is to use TEST_EN pin as selector to mux all different clock domains with single Test Clock. In addition to that you will need SCAN_EN signal to put the design in shift mode for shifting scan data in/out of the chain. This usually drive the SE pin in scannable flop which basically mux your SCAN_INPUT data to flop output instead of D input.

After that, you need to provide two different SDCs( functional and test) during synthesis, to constraint timings at both design modes. In test SDC, you will have to specify separate input/output delay as the test is usually run in ATE with different delay than used in functional applications. You will also have to specify single clock (Test Clock) in your test SDCs. You will have to use "set_case_analaysis TEST_EN 1" to analyze the test mode path for timing in the test mode. Apply any other relevant test mode constraint in your test.sdc.

Then, when doing STA, the timing analysis tool will report if the timing will be met in test mode as well. The DFT insertion also has ability to insert DFT_Lockup_latches to help in meet timing in test mode.

Thanks for the uodates.

From your updates I understood,
i) The 'test_en' will be used for muxing all the internally generated clocks and make the single test clock controllable to all the scan flops.
ii) For synthesis, we need to provide the TEST mode SDC with I/O pin delays , test clock information and test mode constrains if any.

iii) "when doing STA, timing will be met in tet mode." What are the paths the STA has to met during test mode?
is there any other sub modes do the STA has to check timing?

kothandapani said:

iii) "when doing STA, timing will be met in tet mode." What are the paths the STA has to met during test mode?
is there any other sub modes do the STA has to check timing?

Click to expand...

I can think of couple of timing paths.

While shifting in scan data, scannable flops are chain together. The concern here would be hold violation. The data path would be very short because of chain structure between flops, and it has to meet hold timing and not overwrite the current cycle scan data.

The other would be setup. After shifting in scan data, SCAN_EN is deasserted and functional clock pulse is applied in capture mode. The timing constraint would be that data path meet the setup time on scannable flop between SCAN_EN deassertion and functional clock pulse is applied.

Thanks mano I got it.

But one doubt, there are two paths you mentioned,
- scan shift path Q->SI for hold violation, there shold not be any overwrite in one clock cycle.
- in the capture, check for the setup on 'D' path but my question is , will it not be time closed this path during "FUNCTIONAL" STA? or this has to be seperately time closed during test mode STA? Please clarify.

kothandapani said:

- in the capture, check for the setup on 'D' path but my question is , will it not be time closed this path during "FUNCTIONAL" STA? or this has to be seperately time closed during test mode STA? Please clarify.

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Yes, they will be time close during functional STA if your test clock is at same frequency or slower than functional clock. However, sometimes, to reduce test time and eventually testing cost, test clock runs faster(different) than functional clock. In that case, setup time must be met separately in test STA for the test clock which will be different from functional clock.

Thanks for the clarification.

I think I am clear with the test clock and STA during test mode. So this clarifies my first question of this Post.
Coming to the second question which I mentioned in the first page of this post point ii)
As I already mentioned,
""I have two clocks in my design one at running at 80Mhz and another at 500Mhz.
The scope is we are using single test clock for the design""
"ii) How should I handle the at-speed atpg for these two domains?(design has internal PLL)."
Consider the test clock = TCK which runs on ATE = 50 Mhz.
So, for a) DC scan shift = TCK and capture = TCK.
b.0) AC scan shift = TCK but capture = 80 Mhz clock
b.1) AC scan shift = TCK but capture= 500 Mhz clock

For the above point a) I think it clarifies from the past posts as we discussed. But for
points b.0 and b.1 I am not clear on this and how to handle these scenarios? Please help on these points.

kothandapani said:

"ii) How should I handle the at-speed atpg for these two domains?(design has internal PLL)."
Consider the test clock = TCK which runs on ATE = 50 Mhz.
So, for a) DC scan shift = TCK and capture = TCK.
b.0) AC scan shift = TCK but capture = 80 Mhz clock
b.1) AC scan shift = TCK but capture= 500 Mhz clock

For the above point a) I think it clarifies from the past posts as we discussed. But for
points b.0 and b.1 I am not clear on this and how to handle these scenarios? Please help on these points.

Click to expand...

When your capture clock frequency is different than shift clock, what is your clock sequence at ATE? Do you pulse single capture clock per tester cycle?

a) DC scan shift = TCK and capture = TCK.
- This is for stuck-at atpg. It will be of only on capture pulse right when Sscan enable =0; Are ther any thing we can do multile capture ?

b.0) AC scan shift = TCK but capture = 80 Mhz clock
- This is for at-speed with double pulse(one launch pulse and one capture pulse) in broad side case capture clock= 80 Mhz clock.
Are there any multiple capture clock can be applied here?

b.1) AC scan shift = TCK but capture= 500 Mhz clock
- This is for at-speed with double pulse(one launch pulse and one capture pulse) in broad side case capture clock= 500Mhz clock.
Are there any multiple capture clock can be applied here?

Can anyone please clarify the above questions?

Hi ,
Could you please help on my queries I posted above??

kothandapani said:

a) DC scan shift = TCK and capture = TCK.
- This is for stuck-at atpg. It will be of only on capture pulse right when Sscan enable =0; Are ther any thing we can do multile capture ?

b.0) AC scan shift = TCK but capture = 80 Mhz clock
- This is for at-speed with double pulse(one launch pulse and one capture pulse) in broad side case capture clock= 80 Mhz clock.
Are there any multiple capture clock can be applied here?

b.1) AC scan shift = TCK but capture= 500 Mhz clock
- This is for at-speed with double pulse(one launch pulse and one capture pulse) in broad side case capture clock= 500Mhz clock.
Are there any multiple capture clock can be applied here?

Click to expand...

For at-speed, even though you are referring it as launch pulse, after loading in scan data, any functional clock will be capture clock, capturing functional data into flop. It is basically multiple capture clock. The basic idea about applying multiple capture clock is to verify that there is no manufacturing issue that will alter the timing and fail timing in already timing close design. Two capture clock should be enough in verifying this. However, when design has multicycle path, you may have to apply more than 2 functional clock pulse to capture the data.

Hi Mano,
Thanks a lot for clarifying my queries.
So the conclution is two pulse is enough to capture the faults.

Also the logic between the clock domains will not get tested if I test one capture clock at a time.
How can we handle the inter clock domains (logic sits between two clock domains) . These logic will capture the data each other.
How can I test the faults those logic in ATPG?
Please clarify on this.

Hi,
Any one please clarify my query?
How can we handle the inter clock domains (logic sits between two clock domains) . These logic will capture the data each other.
How can I test the faults those logic in ATPG?

Hi Friends,
Any updates on this. Any one please. Discussing the probs/issues is more clear than reading the documents.