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[SOLVED] Difference between a SR "Latch" and a SR "flip-flop"

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navienavnav

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I have already read the "difference between the latch and the flip-flop" questions previously asked on this forum. I do understand the difference as the latch responds to the inputs as long as the pulse is high(or low) i.e, during its duration whereas the flip flop only changes states while clock transition occurs.

But, in that case, what is an SR "flip-flop" ? I know what a SR "latch" is but I cannot find anything such as SR flip-flop in my book (Digital Design by Morris Mano) or on wikipedia. Is there even a thing like SR flip-flop or people mistakenly use the term flip flop for what is a SR latch?
 

Hi,
SR Flip Flop is nothing but SR Latch only. even I had the same confusion but lot of web pages suggested the same.
SR Flip-Flop

Hope this is helpful.
 

On the page that you mentioned, I came across the following :

....The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic circuit possible.
Click to expand...
And here is what I've come across in Digital Design book by Morris Mano :

...The problem with the latch is that it responds to a change in the level of a clock pulse. A positive level response in the enable input allows changes in the output when the input changes while the clock pulse stays at logic 1. The key to the proper operation of a flip-flop is to trigger it only during a signal transition.
Click to expand...

Thus, the words latch and flip-flop mean different things then isn't it a very big error to be using the term interchangeably?
 

navienavnav said:
Thus, the words latch and flip-flop mean different things then isn't it a very big error to be using the term interchangeably?
Click to expand...

You're totally right, but unfortunately these denominations are used rather inhomogeneously. Originally, the difference is that a latch switches input-level-dependent, whereas a flip-flop (FF) switches input-level-change- (or edge-) -dependent -- this is mostly achieved by using a master-slave-FF consisting of 2 FFs in series. But as most FFs -- beside their edge-dependent clock input -- additionally contain a level-dependent set and/or a reset input, they're often called SR-FFs. The naming isn't consistent, unfortunately.
 
see the book by
J. M. Rabaey, A. P. Chandrakasan and B. Nikolic, Digital Integrated Circuits

Given a very good explanation
 

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