Hi All,

I am just stumbled with one of the process that i need to execute for my current assignment?

I tried above method what is mentioned in question but didn't worked out.

Can anyone provide me an easiest way out for following function:

I have to write testcases in verilog for my VHDL based DUT..
This testcases should generate random stimulus(more than stimulus to feed to DUT. for that I have developed one case statement and defined one testcase control register where some configuration parameter for generation of stimulus i am feeding, and my intention is write common function which can read this testcase control register and based on functionality it can produce stimulus.

I have more that 25 testcases to execute, if i will not find best way out, than i need to write lots of code.

So what could be the best way to achieve this functionality in verilog?????