ajanders
Newbie level 1
I am a grad student trying to learn while writing a Tx design in verilog and want to use approx 64k - 128k of my own test data. I know how to use $readmemh(fileID,mem) when in simulation and it works great. However, I want to implement into FPGA (Stratix IV) and want to know how to do that syntactically.
I just need to know the syntax to fill the memory with all the data.
Do I need to actually go element by element?:
or is there a way to:
I have been using Matlab to generate the bit sequence and I was thinking I could just have it write to a dummy module that only has the memory elements I create and `include dummy.v into the design file. I still need to know how I can put all this data into memory.
I just need to know the syntax to fill the memory with all the data.
Code:
reg [15:0] mem[0:2^N-1]; // N is arbitrary
Code:
(some looping struct.) begin
mem[0] <= 10AF;
.
.
mem[2^N-1] <= 039D;
end // would like to avoid since there are over 64k elements
Code:
mem[all] <= contents of file (with some certain syntax);I have been using Matlab to generate the bit sequence and I was thinking I could just have it write to a dummy module that only has the memory elements I create and `include dummy.v into the design file. I still need to know how I can put all this data into memory.
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