# VHDL highest possible integer

1. ## VHDL highest possible integer

A VHDL integer is defined from range -2147483648 to +2147483647.
What if we want to use higher values and still use base 10 numbers to describe our hardware ?
Is it possible to extand this value ?

2. ## Re: VHDL highest possible integer

As far as I know, it is limited to 32-bit and cannot be extended.
Can you tell us more on what you are trying to do?

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3. ## Re: VHDL highest possible integer

Originally Posted by shaiko
A VHDL integer is defined from range -2147483648 to +2147483647.
What if we want to use higher values and still use base 10 numbers to describe our hardware ?
Is it possible to extand this value ?
No you cannot extend the range of integers. You would have to use type signed and forego any calls to the 'to_integer()' function. That would get you up to 2^(2^31) range.

Kevin Jennings

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4. ## Re: VHDL highest possible integer

Does Verilog have the same limiting factor ?

5. ## Re: VHDL highest possible integer

Originally Posted by shaiko
Does Verilog have the same limiting factor ?
No, Verilog does not have the concept of an integer range, only bit widths. An integer type is a short-cut for reg signed [31:0]. SystemVerilog as longint, which is a 64-bit integer. Please note that many system functions assume 32-bit integers, so you need to be aware of that if it matters for what you are trying to do.

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6. ## Re: VHDL highest possible integer

I think its integer range is limited to (2**31)-1, cannot exceed the range.

7. ## Re: VHDL highest possible integer

I think VHDL integer can be extended by using "range" keyword. you can use following code:

SIGNAL integer_1 : integer range 0 to 64;

You can also use the above example for natural also.

8. ## Re: VHDL highest possible integer

Originally Posted by er.akhilkumar
I think VHDL integer can be extended by using "range" keyword. you can use following code:

SIGNAL integer_1 : integer range 0 to 64;

You can also use the above example for natural also.

You cannot extend it beyond the limits already specified. Also, natural is a subtype of integer, so cannot
be extended.

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9. ## Re: VHDL highest possible integer

Yes you are write TrickyDicky, I mistakenly wrote.

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10. ## Re: VHDL highest possible integer

If you ever want to use more range, you should stick with SLV data type. You can have any number of bit width upto 256 bits.

11. ## Re: VHDL highest possible integer

A std_logic_vector is useless for numbers - it is not a numerical type. You want unsigned or signed, and there is no limit on the bit-width, and neither is there with SLV

12. ## Re: VHDL highest possible integer

An std_logic_vector is useless for numbers
What do you mean?. It is not numeral type,okay. But it can be used for numbers, B'coz numbers are data too.As for as I know, integer is a data type which can be used for easier numeral calculations and it is only the compiler that differentiates, but whether it is integer\SLV, it is all same in hardware...

Also, I doubt if the synthesizer might synthesize bit width more than 256 bits though. Because I remember when I was working with Xilinx XST 8.2i, I received error about using bit wdith more than 256 bits in SLV. I think Xilinx uses VHDL-93
Are you sure according to VHDL std?.

13. ## Re: VHDL highest possible integer

The VHDL standard has no limit on the width on any bus, other than the restrictions of the natural type. Why would it?
Std_logic_vector is declared
type std_logic_vector is array(natural range <>) of std_logic;

so you can have a signal like this:
signal my_slv : std_logic_vector(0 to natural'high);

The limit you hit is a Xilinx compiler limit, not a VHDL one.

As for std_logic_vectors and numbers - yes it could be a number, but a std_logic_vector is just a collection of bits, and it was never intedned to be treated as a number. You should use signed/unsigned type instead.

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14. ## Re: VHDL highest possible integer

Originally Posted by shaiko
A VHDL integer is defined from range -2147483648 to +2147483647.
What if we want to use higher values and still use base 10 numbers to describe our hardware ?
Is it possible to extand this value ?
You can skip integers and write a function that takes a string and the wanted bit width as input and returns unsigned or signed. With this method you can use base 10 without a size limit.

If you can accept hexadecimal instead of base 10 there is a simpler solution.
There is no size limit for the x"<hex number>" notation.

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15. ## Re: VHDL highest possible integer

std_match,

Please post an example of such a function

16. ## Re: VHDL highest possible integer

```Code VHDL - [expand]1
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

function decimal_string_to_unsigned(decimal_string: string; wanted_bitwidth: positive) return unsigned is
variable tmp_unsigned: unsigned(wanted_bitwidth-1 downto 0) := (others => '0');
variable character_value: integer;
begin
for string_pos in decimal_string'range loop
case decimal_string(string_pos) is
when '0' => character_value := 0;
when '1' => character_value := 1;
when '2' => character_value := 2;
when '3' => character_value := 3;
when '4' => character_value := 4;
when '5' => character_value := 5;
when '6' => character_value := 6;
when '7' => character_value := 7;
when '8' => character_value := 8;
when '9' => character_value := 9;
when others => report("Illegal number") severity failure;
end case;
tmp_unsigned := resize(tmp_unsigned * 10, wanted_bitwidth);
tmp_unsigned := tmp_unsigned + character_value;
end loop;
return tmp_unsigned;
end decimal_string_to_unsigned;```

Use it like this:
```Code VHDL - [expand]1
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signal xyz: unsigned(32 downto 0);

xyz <= decimal_string_to_unsigned("5000000000", 33);```

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17. ## Re: VHDL highest possible integer

Can I also use it like that ?

Code:
`xyz <= decimal_string_to_unsigned("5000000000", log2_unsigned (5000000000) );`
This will eliminate the need to input the vector length of the integer string

18. ## Re: VHDL highest possible integer

Originally Posted by shaiko
Can I also use it like that ?

Code:
`xyz <= decimal_string_to_unsigned("5000000000", log2_unsigned (5000000000) );`
This will eliminate the need to input the vector length of the integer string
You don't have to use the exact size as the argument. Normally you know the size you are dealing with.

This is OK:

```Code VHDL - [expand]1
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xyz <= decimal_string_to_unsigned("5000000000", 64);
xyz <= decimal_string_to_unsigned("5000000000", xyz'length);```

If you want the minimum width to hold a number, you need to write a new version of log2_unsigned that also take a string as input.
It should be rather straighforward. You an use decimal_string_to_unsigned as a template.
You can use a very large internal tmp_unsigned and at the end look for the leftmost '1'.

If you call it "decimal_string_bits_needed" you need to to something like this:
```Code VHDL - [expand]1
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constant my_large_number: string := "5000000000";
signal xyz: unsigned(decimal_string_bits_needed(my_large_number)-1 downto 0);

xyz <= decimal_string_to_unsigned(my_large_number, xyz'length);```

One good improvement to "decimal_string_to_unsigned" is get an error or warning if the number doesn't fit in the specified number of bits.

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19. ## Re: VHDL highest possible integer

If you want the minimum width to hold a number, you need to write a new version of log2_unsigned that also take a string as input.
Why?
Why can't I use the original log function?

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20. ## Re: VHDL highest possible integer

Originally Posted by shaiko
Why?
Why can't I use the original log function?
The input to the original function is probably integer or a subtype of integer, so it doesn't work for the numbers we are discussing now.

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