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5th April 2012, 16:13 #1
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VHDL highest possible integer
A VHDL integer is defined from range 2147483648 to +2147483647.
What if we want to use higher values and still use base 10 numbers to describe our hardware ?
Is it possible to extand this value ?

5th April 2012, 16:52 #2
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Re: VHDL highest possible integer
As far as I know, it is limited to 32bit and cannot be extended.
Can you tell us more on what you are trying to do?
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5th April 2012, 19:05 #3
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5th April 2012, 20:21 #4
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Re: VHDL highest possible integer
Does Verilog have the same limiting factor ?

5th April 2012, 20:42 #5
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Re: VHDL highest possible integer
No, Verilog does not have the concept of an integer range, only bit widths. An integer type is a shortcut for reg signed [31:0]. SystemVerilog as longint, which is a 64bit integer. Please note that many system functions assume 32bit integers, so you need to be aware of that if it matters for what you are trying to do.
Dave Rich
Senior Verification Consultant
Mentor Graphics Corporation
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6th April 2012, 05:35 #6
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Re: VHDL highest possible integer
I think its integer range is limited to (2**31)1, cannot exceed the range.
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30th May 2012, 13:58 #7
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Re: VHDL highest possible integer
I think VHDL integer can be extended by using "range" keyword. you can use following code:
SIGNAL integer_1 : integer range 0 to 64;
You can also use the above example for natural also.

30th May 2012, 14:11 #8
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30th May 2012, 14:17 #9
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Re: VHDL highest possible integer
Yes you are write TrickyDicky, I mistakenly wrote.

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31st May 2012, 15:34 #10
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Re: VHDL highest possible integer
If you ever want to use more range, you should stick with SLV data type. You can have any number of bit width upto 256 bits.

31st May 2012, 15:54 #11
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Re: VHDL highest possible integer
A std_logic_vector is useless for numbers  it is not a numerical type. You want unsigned or signed, and there is no limit on the bitwidth, and neither is there with SLV

1st June 2012, 09:54 #12
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Re: VHDL highest possible integer
An std_logic_vector is useless for numbers
Also, I doubt if the synthesizer might synthesize bit width more than 256 bits though. Because I remember when I was working with Xilinx XST 8.2i, I received error about using bit wdith more than 256 bits in SLV. I think Xilinx uses VHDL93
Are you sure according to VHDL std?.

1st June 2012, 11:17 #13
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Re: VHDL highest possible integer
The VHDL standard has no limit on the width on any bus, other than the restrictions of the natural type. Why would it?
Std_logic_vector is declared
type std_logic_vector is array(natural range <>) of std_logic;
so you can have a signal like this:
signal my_slv : std_logic_vector(0 to natural'high);
The limit you hit is a Xilinx compiler limit, not a VHDL one.
As for std_logic_vectors and numbers  yes it could be a number, but a std_logic_vector is just a collection of bits, and it was never intedned to be treated as a number. You should use signed/unsigned type instead.
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1st June 2012, 12:03 #14
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Re: VHDL highest possible integer
You can skip integers and write a function that takes a string and the wanted bit width as input and returns unsigned or signed. With this method you can use base 10 without a size limit.
If you can accept hexadecimal instead of base 10 there is a simpler solution.
There is no size limit for the x"<hex number>" notation.
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1st June 2012, 19:00 #15
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Re: VHDL highest possible integer
std_match,
Please post an example of such a function

1st June 2012, 21:18 #16
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Re: VHDL highest possible integer
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; function decimal_string_to_unsigned(decimal_string: string; wanted_bitwidth: positive) return unsigned is variable tmp_unsigned: unsigned(wanted_bitwidth1 downto 0) := (others => '0'); variable character_value: integer; begin for string_pos in decimal_string'range loop case decimal_string(string_pos) is when '0' => character_value := 0; when '1' => character_value := 1; when '2' => character_value := 2; when '3' => character_value := 3; when '4' => character_value := 4; when '5' => character_value := 5; when '6' => character_value := 6; when '7' => character_value := 7; when '8' => character_value := 8; when '9' => character_value := 9; when others => report("Illegal number") severity failure; end case; tmp_unsigned := resize(tmp_unsigned * 10, wanted_bitwidth); tmp_unsigned := tmp_unsigned + character_value; end loop; return tmp_unsigned; end decimal_string_to_unsigned;
Use it like this:
Code VHDL  [expand] 1 2 3
signal xyz: unsigned(32 downto 0); xyz <= decimal_string_to_unsigned("5000000000", 33);
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2nd June 2012, 16:47 #17
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Re: VHDL highest possible integer
Can I also use it like that ?
Code:xyz <= decimal_string_to_unsigned("5000000000", log2_unsigned (5000000000) );

2nd June 2012, 17:49 #18
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Re: VHDL highest possible integer
You don't have to use the exact size as the argument. Normally you know the size you are dealing with.
This is OK:
Code VHDL  [expand] 1 2
xyz <= decimal_string_to_unsigned("5000000000", 64); xyz <= decimal_string_to_unsigned("5000000000", xyz'length);
If you want the minimum width to hold a number, you need to write a new version of log2_unsigned that also take a string as input.
It should be rather straighforward. You an use decimal_string_to_unsigned as a template.
You can use a very large internal tmp_unsigned and at the end look for the leftmost '1'.
If you call it "decimal_string_bits_needed" you need to to something like this:
Code VHDL  [expand] 1 2 3 4
constant my_large_number: string := "5000000000"; signal xyz: unsigned(decimal_string_bits_needed(my_large_number)1 downto 0); xyz <= decimal_string_to_unsigned(my_large_number, xyz'length);
One good improvement to "decimal_string_to_unsigned" is get an error or warning if the number doesn't fit in the specified number of bits.
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2nd June 2012, 18:19 #19
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Re: VHDL highest possible integer
If you want the minimum width to hold a number, you need to write a new version of log2_unsigned that also take a string as input.
Why can't I use the original log function?

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2nd June 2012, 18:39 #20
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