For reporting area in synthesis

I have following question:

When we report area in synthesis, a varities of areas are defined. Can you please let me know about the definition of various types of areas that is usually present in a stnthesis area report?

1. How is net area defined?

2. How is total area defined? We get total area in a synthesis report.

3. What are the other area other than the cell area that a synthesis tool report? How are they defined?

4. How is Leaf Instance Count defined?

5. How is Sequential Instance Count defined?

6. How is Combinational Instance Count defined?

7. How is Hierarchical Instance Count defined?

Regards

I don't know what synthesis tool you're using and I'm actually not looking at any synthesis tool manuals at the moment but I'll try to answer some of these.

1. The net area is probably a figure relating to the amount of routing resources used. I'm guessing this defined in the technology section of the library you're using and it's probably just an estimate detailed routing information isn't available just after synthesis.

2. It's probably the sum of the standard cell area, macro and memory area. Possibly the net area depending on the synthesis tool.

3. Memory and macro instances all contribute to the total area. Maybe halo and DRC area is included too?

4. Leaf cells are cells that can't be broken down any further. Like AND gates and INV gates. These take up real area on the chip die.

5. A summation of the sequential cells in the design: Flops, latches, etc.

6. The non-sequential cells: NANDs, BUFs, etc.

7. Hierarchical instances aren't physical cells but named logical partitions of the design.

Your synthesis manual should definitely have a detailed description of where it gets the figures it reports.

HTH

Hi

Gliss your answers are not completely answering my questions.

Regards

All of them? Like leaf cells vs hierarchical cells? A hierarchical cell is a cell made up of leaf cells and possibly other hierarchical cells. A leaf cell on the other hand doesn't instantiate any other instances. When the netlist is flattened, hierarchical cells no longer exist. Does that help explain things further? Let me know exactly what isn't clear.

The answer to the following question are not proper as you are staing probably. I want a sure answer if possible. Is it that the answers of my questions other than the two below are also probable?

1. How is net area defined?

2. How is total area defined? We get total area in a synthesis report.

Net area is defined by the tech library you're using, the # of interconnections, the metal layers used for routing, and the wire lengths. But pre place & route, this is not a useful figure I would imagine.

Can you surely answer these questions:

1. How is net area defined?

2. How is total area defined? We get total area in a synthesis report?

Last time you provided a unsure/probable answer.

The net area is answered in posted #6. The total area is the standard cell area and the macro/memory area. The net area and the total area units are defined by the tool.
What synthesis tool are you using?

gliss said:

What synthesis tool are you using?

Click to expand...

I use both DC and RTL Compiler. Which field do you work in? Do you work in fabrication? Why did you say your answers are probable when you wrote the answer first time? Were not you sure of the answers then? How did you made yourself sure of that?


I have another question as stated below:

What is the command that will report the chip utilization while doing synthesis?

Regards