honigal
Newbie level 3
Hi,
I'm using an ISM band 2.4GHz transceiver P/N:ML2724 from RFMD for high speed data communication. this transceiver is 1.536Mbps bandwidth capable with no ISI mitigation techniques inside the chip. However, an 'AOUT' signal which is the output of the 2 level FSK demodulator is available for external use such as bit slicing.
attaching the link to ML2724 datasheet with block diagram for reference:
https://www.rfmd.com/CS/Documents/ML2724_ML2724SPACEDatasheet.pdf
I would like to sample this AOUT signal with a high speed ADC and feed it to an FPGA there i will equalize this signal and do some extra receive processing.
My questions:
Thank you all.
Alex
I'm using an ISM band 2.4GHz transceiver P/N:ML2724 from RFMD for high speed data communication. this transceiver is 1.536Mbps bandwidth capable with no ISI mitigation techniques inside the chip. However, an 'AOUT' signal which is the output of the 2 level FSK demodulator is available for external use such as bit slicing.
attaching the link to ML2724 datasheet with block diagram for reference:
https://www.rfmd.com/CS/Documents/ML2724_ML2724SPACEDatasheet.pdf
I would like to sample this AOUT signal with a high speed ADC and feed it to an FPGA there i will equalize this signal and do some extra receive processing.
My questions:
- Does this sound like a good plan?
- Which Equalization technique will fit here?
- There is a "hard limiter" just before the F to V function (see attached block diagram). Does this means adding equalization maybe late and thus futile?
- With what data should I train my equalizer? (currently my packet format is:
| 101010...1010 | 64 bits word with good auto correlation characteristics (for start of frame purposes) | Payload | CRC |. my guess I should change my ZOZO to PN and train it with these preamble bits. - How can I tell how much improvement should I expect after equalization?
Thank you all.
Alex
