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20th March 2012, 21:26 #1
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1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
Hello everyone,
I am trying to implement a Kalman Filter for tracking ball in Spartan6 FPGA in 32bit fixed point. I have used fixed_pkg_c.vhd which is in ieee_proposd library for the fixed point operatons. Then I defined some functions for matrix operations which are working fine individually. Now, when I am trying to synthesize this whole code, I am having two problems.
1. I am having this warning for every bits of x, x_predicted, P_predicted, K, P matrices :
"WARNING:Xst:737  Found 1bit latch for signal <x<0><0><15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems."
(This is the warning for x<0><0><15>, same is the warning for every other bits of matrices x, x_predicted, P_predicted, K, P).
2. Finally the synthsis stops with an error telling that memory shortge is occurring. Following is the whole error message :
"================================================= ========================
* Low Level Synthesis *
================================================== =======================
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <FSM_0> on signal <pr_state[1:2]> with gray encoding.

State  Encoding

state0  00
state1  01
state2  11
state3  10

Optimizing unit <kalman_try2> ...
ERROR:Portability:3  This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 2085956 kb. You can try increasing your system's physical or virtual memory. If you are using a Win32 system, you can increase your application memory from 2GB to 3GB using the /3G switch in your boot.ini file. For more information on this, please refer to Xilinx Answer Record #14932. For technical support on this issue, you can open a WebCase with this project atta ched at http://www.xilinx.com/support."
I think there is some bug in my code and so it is showing this error. Also, when I removed the last equation "P <= matmul_6x6_6x6(temp5, P_predicted);" , the rest part is synthesized normally. I am not being able to understand this strange problem.
If anybody is having any idea about the mistake in the code plzz help me. Here is my code (without the functions, as the functions are very long I have not included them). Thanking you in advance... :)
This is the pckage my_package.vhd :
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
library IEEE; use IEEE.STD_LOGIC_1164.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; package my_package is constant ufixed_matrix_high : INTEGER := 15; constant ufixed_matrix_low : INTEGER := 16; constant ufixed_one : ufixed (1 downto 0) := "01";  1.0 constant zero : ufixed (15 downto 16) := "00000000000000000000000000000000"; constant one : ufixed (15 downto 16) := "00000000000000010000000000000000"; constant x1 : ufixed (15 downto 16) := "00000100000000000000000000000000"; subtype ufixedr is ufixed (ufixed_matrix_high downto ufixed_matrix_low); type ufixed_matrix is array (NATURAL range <>, NATURAL range <>) of ufixedr; type ufixed_vector is array (NATURAL range <>) of ufixedr; end my_package; This is the main code (except the functions which are very long, so I haven't included them here) : library IEEE; use IEEE.STD_LOGIC_1164.ALL; library work; use work.my_package.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; entity kalman_try2 is port( rst,clk : in std_logic; y_measured : in ufixed_matrix (0 to 1, 0 to 0); op : out ufixed(15 downto 16) ); end kalman_try2; architecture Behavioral of kalman_try2 is constant A : ufixed_matrix (0 to 5, 0 to 5) := ((one,one,one,zero,one,zero),(zero,one,zero,one,zero,one),(zero,zero,one,zero,one,zero),(zero,zero,zero,one,zero,one),(zero,zero,zero,zero,one,zero),(zero,zero,zero,zero,zero,one)); constant H : ufixed_matrix (0 to 1, 0 to 5) := ((one,zero,one,zero,one,zero),(zero,one,zero,one,zero,one)); signal x_predicted : ufixed_matrix (0 to 5, 0 to 0); signal x : ufixed_matrix (0 to 5, 0 to 0);:= ((mc/2),(mr/2),(zero),(zero),(zero),(zero)); signal Bu : ufixed_matrix (0 to 5, 0 to 0);:=((zero),(zero),(zero),(zero),(zero),(zero)); signal P_predicted : ufixed_matrix (0 to 5, 0 to 5); signal P : ufixed_matrix (0 to 5, 0 to 5):= x1 * eye(6,6); k1 = 1000 constant Q : ufixed_matrix (0 to 5, 0 to 5):= one * eye(6,6); k2 = 0.01 constant R : ufixed_matrix (0 to 1, 0 to 1):= ((one,zero),(zero,one)); signal K : ufixed_matrix (0 to 5, 0 to 1); constant mc : ufixed (15 downto 16) := "00000010000000000000000000000000"; constant mr : ufixed (15 downto 16) := "00000001000000000000000000000000"; signal state : integer range 0 to 3 := 0; type statex is (state0, state1, state2, state3); signal pr_state, nxt_state : statex; begin process(rst,clk) begin if (rst = '1') then pr_state <= state0; elsif (clk'event and clk = '1') then pr_state <= nxt_state; end if; end process; process(pr_state) variable temp1 : ufixed_matrix (0 to 5, 0 to 5); variable temp2 : ufixed_matrix (0 to 5, 0 to 1); variable temp3 : ufixed_matrix (0 to 1, 0 to 1); variable temp4 : ufixed_matrix (0 to 1, 0 to 0); variable temp5 : ufixed_matrix (0 to 5, 0 to 5); begin case pr_state is when state0 => x(0,0) <= mc; x(1,0) <= mr; x(2,0) <= zero; x(3,0) <= zero; x(4,0) <= zero; x(5,0) <= zero; op <= zero; nxt_state <= state1 ; when state1 => x_predicted <= A*x ; Bu;  predication of next state variable temp1 := matmul_6x6_6x6(A ,P);  preidiction of state varince matrix (error in estimation) P_predicted <= matmul_6x6_6x6(temp1,trans(A)) + Q; op <= P_predicted(0,0); nxt_state <= state2; when state2 => temp2 := matmul_6x6_6x2(P_predicted ,trans(H));  update the value of kalman gain temp3 := matmul_2x6_6x2(H ,temp2) + R ; K <= matmul_6x2_2x2(temp2,temp3); op <= K(0,0); nxt_state <= state3; when state3 => update current state estimate as sum of current state prediction & scaled error in current state prediction temp4 := y_measured  H*x_predicted; x <= x_predicted + K * temp4;  update state varince matrix based on predicted state variance matrix temp5 := eye(6,6)matmul_6x2_2x6(K, H); P <= matmul_6x6_6x6(temp5, P_predicted); op <= x(0,0); nxt_state <= state1; end case; end process; end Behavioral;
Last edited by alexan_e; 20th March 2012 at 22:43. Reason: added SYNTAX tags

20th March 2012, 23:57 #2
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
You need to assign ALL your outputs in every branch of the case statement, otherwise you'll get latches. You can use default assignments to make this easier.
Also, you probably don't need an async reset.
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21st March 2012, 15:39 #3
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
Thank you very much...but can u give me any idea about the 2nd problem as why the code is showing insufficient memory error, though it is synthesized easily with the last equation removed???

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23rd March 2012, 02:15 #4
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
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23rd March 2012, 07:33 #5
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
Ok,I have solved this problem a bit by doing my operation in 16 bit in place of 32bits which significantly lowered down my computational burden. But now when I synthesized the program it was showing more slice LUT and DSP48E block requirement than what spartan6 actually has. So, I tried to make my code more sequential so that LUT and DSP block utilization reduces. Then my slice LUT utilization decreased from 260% to 72% but somehow DSP48E block usage increased from 196% to 434%.
Although by serializing I reduced no. of operations(multiplication , addition and subtraction) in one clock cycle significantly , then any idea why is my DSP48E count increasing??? Thank u in advance...:)

23rd March 2012, 15:58 #6
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
Nice!
That will depend on your code, synthesis/map options, and the way you configured any cores used.
It will probably take some significant effort to get that large of a design to fit on that device and still meet timing.

3rd April 2012, 09:21 #7
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
Could you give me the full code, i am doing my final year project.

3rd April 2012, 09:40 #8
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Re: 1bit latch warning and memory error in Kalman Filter Implementation in Spartan6
Please don't make requests for help in private using PM. Create a thread in the forum so that other members can benefit from the posted answers.
Consider reading this before posting : How To Ask Questions The Smart Way

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3rd April 2012, 17:25 #9
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