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setup violations @(min delays) and hold violations @(max delays)

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ivlsi

ivlsi

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Hello All,

Is it possible that the setup violations occur in the best-case analysis (min delays) and hold violations in the worst-case analysis (max delays)?

Thank you!
 

My opinion is that it is not possible. Setup time is optimize using worst-case timing, so if the design operating in best-case, not setup violations will exist. The same for hold time which is not possible.
 

hairo said:
My opinion is that it is not possible. Setup time is optimize using worst-case timing, so if the design operating in best-case, not setup violations will exist. The same for hold time which is not possible.
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This is only true for vanilla designs which have plenty of slack and behave nicely across corners. But in reality for complex designs with tight margins (post route), you can see hold vios in max corner and vice versa. There is no reason as to why you should not see such violations.
 
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    ivlsi

    ivlsi

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Great answer, matter! Even on min-delays a pure logic might be so big so that its propagation delay might be larger than a clock cycle. On other hand, skew on the clocks might be so big so that hold delay occur even on max delays!
 

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