Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] asking about values in the Synthesis report

Status
Not open for further replies.
S

sharkya2a

Junior Member level 1
Joined
Nov 19, 2011
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,395
hi all,
after the Synthesis, i can see this values at the end of the Synthesis report

Minimum period: 9.079ns (Maximum Frequency: 110.139MHz)
Minimum input arrival time before clock: 4.806ns
Maximum output required time after clock: 3.554ns
Maximum combinational path delay: No path found

what do these lines in the synthesis report tell me?

can any one tell me what "Minimum period: 9.079ns" exactly means ?

Thanx in advance (^__^)
 

The timing analyser recons that the max clock speed for your design is 110 Mhz. (I assume you did not provide a timing file?)

The others are to do with worst case setup and hold times.
 

TrickyDicky said:
The timing analyser recons that the max clock speed for your design is 110 Mhz. (I assume you did not provide a timing file?)

The others are to do with worst case setup and hold times.
Click to expand...



thank you
but what "Minimum period: 9.079ns" exactly means ?

best regards
 

That is the worst case register to register delay in your compiled design.
 

what i know that,

- Frequency means number of clock cycles per second.
- Clock Period means the time needed for each clock cycle.

is that correct or not ?

best regards
 

In synchronous digital design, you typically have this: register : some logic : register

How fast can a design be run? In other words, what is the maximum clock frequency that the circuit can operate at. This is determined by the delay between the flip flops which is what the Minimum period: 9.079ns means.
 

rreddy said:
In synchronous digital design, you typically have this: register : some logic : register

How fast can a design be run? In other words, what is the maximum clock frequency that the circuit can operate at. This is determined by the delay between the flip flops which is what the Minimum period: 9.079ns means.
Click to expand...

thanx (^__^)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top