allanvv
Advanced Member level 4
I'm using cells to create the VDD/VSS power grid. The bottommost cell in the hierarchy is just two metal lines crossing each other with a via. Since there are no instances in the layout or schematic, just wires, LVS fails on this cell:
ERROR: Nothing in source.
ERROR: Nothing in layout.
ERROR: Corresponding cells could not be identified.
There aren't any metal layer resistor layout cells in the PDK, only schematic level ones for simulation. How should I fix this? The upper hierarchy cells that use this cell fail as well. I suppose I can create it all the way upward and then flatten it at the topmost cell, but I'd rather not have to do that.
edit: figured it out, using the SVRF command: LVS BOX cell_name
ERROR: Nothing in source.
ERROR: Nothing in layout.
ERROR: Corresponding cells could not be identified.
There aren't any metal layer resistor layout cells in the PDK, only schematic level ones for simulation. How should I fix this? The upper hierarchy cells that use this cell fail as well. I suppose I can create it all the way upward and then flatten it at the topmost cell, but I'd rather not have to do that.
edit: figured it out, using the SVRF command: LVS BOX cell_name
Last edited: