Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

error in synopsys custom designer in LVS

Status
Not open for further replies.
S

sandeep_sggs

Full Member level 2
Joined
Jan 21, 2008
Messages
140
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Location
india
Activity points
2,226
dear all,
i have implemented an inverter in synopsys custom designer. and now i am trying to do DRC, LVS and Parasitic extraction. Problem is when i do the DRC check then i could pass it. but when i try to go for LVS, i get errors. can any body tell me whats wrong with my procedure. i am attaching the relevant files.
I using synopsys for the first time
 

Attachments

  • Screenshot-0 Custom Designer Console(1).png
    Screenshot-0 Custom Designer Console(1).png
    118 KB · Views: 101
  • Screenshot-LVS Setup and Run.png
    Screenshot-LVS Setup and Run.png
    43.9 KB · Views: 100
  • synopsys.cshrc.doc
    970 bytes · Views: 49

sandeep_sggs said:
I using synopsys for the first time
Click to expand...

... and I've never used it, so I don't know if my following note will be helpful:

With C@dence LVS tools, the extracted view is called extracted, so in the LVS Setup and Run window in the Layout section, the View type should be extracted, not layout. May be this is similar with your tool?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top