Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Subthreshold conduction !!!

Status
Not open for further replies.
J

jeet_asic

Full Member level 3
Joined
Nov 18, 2011
Messages
156
Helped
20
Reputation
40
Reaction score
19
Trophy points
1,298
Location
Bangalore
Activity points
2,196
CMOS :

If we reduce threshold voltage , subthreshold conduction increases ??? why ? .. if we reduce Vgs below Vt voltage , current doesn't go to zero abruptly , it falls exponentially. So if i reduce Vt , how Subthreshold conduction increases , it should decrease.:?:
 

Please refer to the Weste & Harris CMOS VLSI Design.
You can find out why subthreshold current increases with Threshold voltage decreasing.
 

Sir , i did explore Weste , but i didn't get clear explanation. I have been looking for this doubt for longtime now. But no success. Sir , can you provide some links or any material which clearly explains the reason.
Oveis.Gharan said:
Please refer to the Weste & Harris CMOS VLSI Design.
You can find out why subthreshold current increases with Threshold voltage decreasing.
Click to expand...
 

Please read the below paper. You can find a lot of thing through the text.
S. K. Gupta, et al., "Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective," Proceedings of the IEEE, vol. 98, 2010.
Could you access IEEExplore?

Feel free to ask more ...
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top