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Summing an unpacked array of real numbers for a testbench using system verilog

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BartlebyScrivener

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Hi. In my testbench I have an array

Code: 
 real batchTotal [10];

which I am trying to total up into the real number.

Code: 
real total

by using the following code

Code: 
total <= batchTotal.sum();

which compiles fine, however when I try and simulate I get the following error.

Code: 
# ** Fatal: (vsim-8144) C:/altera/11.0/networkTest.sv(336): Reduction methods require packed elem. values.
#    Time: 0 ps  Iteration: 1  Process: /networkTest/#ALWAYS#330 File: C:/altera/11.0/networkTest.sv
# Fatal error in Module networkTest at C:/altera/11.0/networkTest.sv line 336
# 
# HDL call sequence:
# Stopped at C:/altera/11.0/networkTest.sv 336 Module networkTest
#

Any ideas? I am confused because the code worked when I was using int value type, but as I am using a division to get the values I want to use real type. When I changed from int to real, it stopped working. Thanks in advance!
 

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