jaya sree
Member level 3
Hai ,
I have clock transition violations after Clock tree synthesis is over.skew and insertion delay are under control. Is there any command in encounter or Ic compiler to clone a clock net to fix tran violation?
I have clock transition violations after Clock tree synthesis is over.skew and insertion delay are under control. Is there any command in encounter or Ic compiler to clone a clock net to fix tran violation?