Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

command to clone clock net to fix clock transition violations

Status
Not open for further replies.
J

jaya sree

Member level 3
Joined
Nov 9, 2009
Messages
55
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
india
Activity points
1,791
Hai ,

I have clock transition violations after Clock tree synthesis is over.skew and insertion delay are under control. Is there any command in encounter or Ic compiler to clone a clock net to fix tran violation?
 

I am also going through the same issue with ICC(2011.09) in my current project. Please post any ideas/suggestions for debugging this issue.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top