Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Reference voltage and full scale range in ADC

Status
Not open for further replies.
S

shico90

Junior Member level 2
Joined
Apr 7, 2011
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,418
Hello, I was asking about the reference voltage and how to choose its value in the design of ADC supposing I have VDD and what is its relation with the full scale input in dBm and Does it relate in any way with the bias voltage of the ADC?
 

Assuming the ref voltage large enough.
I think the ref voltage should as close to the full scale as possible.
Because the larger the input signal value comparing to the ref, the higher SNR.
 

The smaller v ref results more resolution but less input measurment
The bigger v ref results less resolution but more input measurment
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top