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A delayed clock output in VHDL

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1nandha

1nandha

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My logic is to get output after a particular number of clocks, its not an delayed output but I have to get the results of the delayed clocks.

For eg: if count=2, for every 2nd clock I should get its corresponding output and not other clocks result.
if count=5, for every 5th clock I should get its corresponding output and not other clocks result.

Please guide.
 

so you want to set a parameter that changes the timing on a clock enable?
 

1nandha said:
My logic is to get output after a particular number of clocks, its not an delayed output but I have to get the results of the delayed clocks.

For eg: if count=2, for every 2nd clock I should get its corresponding output and not other clocks result.
if count=5, for every 5th clock I should get its corresponding output and not other clocks result.

Please guide.
Click to expand...

Code: 
constant MAX_COUNT: natural := ??; -- Whatever is your maximum, based on your post it would be 5
signal clock_count: natural range 0 to MAX_COUNT;
signal This_Would_Be_The_Time_To_Sample: std_ulogic;
begin
  process
  begin
    wait until rising_edge(clock);
      if (Initialize = '1') -- Maybe you want to get the counter into a known state at startup, maybe not
      or (count = 1) then
        count <= My_Max_Count;  -- My_Max_Count would be an input that you set that is set to whatever you want to count from.
                                            -- In your post, you mentioned 2 or 5
     else
        count <= count - 1;
    end if;
  end process;

  This_Would_Be_The_Time_To_Sample <= '1' when (count = 1) else '0';

Should be enough guidance to get you going

Kevin Jennings
 
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