Problem Library funtion Strtok in Hi-tech c

//Chip Settings
__PROG_CONFIG(CONFIG1L,0x00);
__PROG_CONFIG(CONFIG1H,0x00); //Oscillator Selection bits as "XT"
__PROG_CONFIG(CONFIG2L,0x01);
__PROG_CONFIG(CONFIG2H,0x00); //WDT Disable
__PROG_CONFIG(CONFIG3H,0x00); //MCLR disable
__PROG_CONFIG(CONFIG4L,0x00);
__PROG_CONFIG(CONFIG5L,0x00);
__PROG_CONFIG(CONFIG5H,0x00);
__PROG_CONFIG(CONFIG6L,0x00);
__PROG_CONFIG(CONFIG6H,0x00);
__PROG_CONFIG(CONFIG7L,0x00);
__PROG_CONFIG(CONFIG7H,0x00);

__CONFIG(1, RC);
__CONFIG(2, BW8 & PWRTDIS & WDTPS1 & WDTEN);
__CONFIG(4, STVRDIS);
...
...
...

// Config Register: CONFIG1L
// PLL Prescaler Selection bits
// Divide by 12 (48 MHz oscillator input)
#define PLLDIV_12            0xFFF8 
// Divide by 10 (40 MHz oscillator input)
#define PLLDIV_10            0xFFF9 
// Divide by 6 (24 MHz oscillator input)
#define PLLDIV_6             0xFFFA 
// Divide by 5 (20 MHz oscillator input)
#define PLLDIV_5             0xFFFB 
// Divide by 4 (16 MHz oscillator input)
#define PLLDIV_4             0xFFFC 
// Divide by 3 (12 MHz oscillator input)
#define PLLDIV_3             0xFFFD 
// Divide by 2 (8 MHz oscillator input)
#define PLLDIV_2             0xFFFE 
// No prescale (4 MHz oscillator input drives PLL directly)
#define PLLDIV_1             0xFFFF 
// System Clock Postscaler Selection bits
// [Primary Oscillator Src: /4][96 MHz PLL Src: /6]
#define CPUDIV_OSC4_PLL6     0xFFE7 
// [Primary Oscillator Src: /3][96 MHz PLL Src: /4]
#define CPUDIV_OSC3_PLL4     0xFFEF 
// [Primary Oscillator Src: /2][96 MHz PLL Src: /3]
#define CPUDIV_OSC2_PLL3     0xFFF7 
// [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
#define CPUDIV_OSC1_PLL2     0xFFFF 
// USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
// USB clock source comes from the 96 MHz PLL divided by 2
#define USBDIV_2             0xFFDF 
// USB clock source comes directly from the primary oscillator block with no postscale
#define USBDIV_1             0xFFFF 


// Config Register: CONFIG1H
// Oscillator Selection bits
// HS oscillator, PLL enabled (HSPLL)
#define FOSC_HSPLL_HS        0xF4FF 
// HS oscillator (HS)
#define FOSC_HS              0xF6FF 
// Internal oscillator, HS oscillator used by USB (INTHS)
#define FOSC_INTOSC_HS       0xF1FF 
// Internal oscillator, XT used by USB (INTXT)
#define FOSC_INTOSC_XT       0xF0FF 
// Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)
#define FOSC_INTOSC_EC       0xF3FF 
// Internal oscillator, port function on RA6, EC used by USB (INTIO)
#define FOSC_INTOSCIO_EC     0xF2FF 
// EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)
#define FOSC_ECPLL_EC        0xFDFF 
// EC oscillator, PLL enabled, port function on RA6 (ECPIO)
#define FOSC_ECPLLIO_EC      0xFCFF 
// EC oscillator, CLKO function on RA6 (EC)
#define FOSC_EC_EC           0xFFFF 
// EC oscillator, port function on RA6 (ECIO)
#define FOSC_ECIO_EC         0xFEFF 
// XT oscillator, PLL enabled (XTPLL)
#define FOSC_XTPLL_XT        0xF8FF 
// XT oscillator (XT)
#define FOSC_XT_XT           0xFAFF 
// Fail-Safe Clock Monitor Enable bit
// Fail-Safe Clock Monitor enabled
#define FCMEN_ON             0xBFFF 
// Fail-Safe Clock Monitor disabled
#define FCMEN_OFF            0xFFFF 
// Internal/External Oscillator Switchover bit
// Oscillator Switchover mode enabled
#define IESO_ON              0x7FFF 
// Oscillator Switchover mode disabled
#define IESO_OFF             0xFFFF 


// Config Register: CONFIG2L
// Power-up Timer Enable bit
// PWRT disabled
#define PWRT_OFF             0xFFFF 
// PWRT enabled
#define PWRT_ON              0xFFFE 
// Brown-out Reset Enable bits
// Brown-out Reset enabled in hardware only (SBOREN is disabled)
#define BOR_ON               0xFFFF 
// Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
#define BOR_ON_ACTIVE        0xFFFD 
// Brown-out Reset enabled and controlled by software (SBOREN is enabled)
#define BOR_SOFT             0xFFFB 
// Brown-out Reset disabled in hardware and software
#define BOR_OFF              0xFFF9 
// Brown-out Reset Voltage bits
// Minimum setting
#define BORV_3               0xFFFF 
#define BORV_2               0xFFF7 
#define BORV_1               0xFFEF 
// Maximum setting
#define BORV_0               0xFFE7 
// USB Voltage Regulator Enable bit
// USB voltage regulator enabled
#define VREGEN_ON            0xFFDF 
// USB voltage regulator disabled
#define VREGEN_OFF           0xFFFF 


// Config Register: CONFIG2H
// Watchdog Timer Enable bit
// WDT enabled
#define WDT_ON               0xFFFF 
// WDT disabled (control is placed on the SWDTEN bit)
#define WDT_OFF              0xFEFF 
// Watchdog Timer Postscale Select bits
// 1:32768
#define WDTPS_32768          0xFFFF 
// 1:16384
#define WDTPS_16384          0xFDFF 
// 1:8192
#define WDTPS_8192           0xFBFF 
// 1:4096
#define WDTPS_4096           0xF9FF 
// 1:2048
#define WDTPS_2048           0xF7FF 
// 1:1024
#define WDTPS_1024           0xF5FF 
// 1:512
#define WDTPS_512            0xF3FF 
// 1:256
#define WDTPS_256            0xF1FF 
// 1:128
#define WDTPS_128            0xEFFF 
// 1:64
#define WDTPS_64             0xEDFF 
// 1:32
#define WDTPS_32             0xEBFF 
// 1:16
#define WDTPS_16             0xE9FF 
// 1:8
#define WDTPS_8              0xE7FF 
// 1:4
#define WDTPS_4              0xE5FF 
// 1:2
#define WDTPS_2              0xE3FF 
// 1:1
#define WDTPS_1              0xE1FF 


// Config Register: CONFIG3H
// CCP2 MUX bit
// CCP2 input/output is multiplexed with RC1
#define CCP2MX_ON            0xFFFF 
// CCP2 input/output is multiplexed with RB3
#define CCP2MX_OFF           0xFEFF 
// PORTB A/D Enable bit
// PORTB<4:0> pins are configured as analog input channels on Reset
#define PBADEN_ON            0xFFFF 
// PORTB<4:0> pins are configured as digital I/O on Reset
#define PBADEN_OFF           0xFDFF 
// Low-Power Timer 1 Oscillator Enable bit
// Timer1 configured for low-power operation
#define LPT1OSC_ON           0xFBFF 
// Timer1 configured for higher power operation
#define LPT1OSC_OFF          0xFFFF 
// MCLR Pin Enable bit
// MCLR pin enabled; RE3 input pin disabled
#define MCLRE_ON             0xFFFF 
// RE3 input pin enabled; MCLR pin disabled
#define MCLRE_OFF            0x7FFF 


// Config Register: CONFIG4L
// Stack Full/Underflow Reset Enable bit
// Stack full/underflow will cause Reset
#define STVREN_ON            0xFFFF 
// Stack full/underflow will not cause Reset
#define STVREN_OFF           0xFFFE 
// Single-Supply ICSP Enable bit
// Single-Supply ICSP enabled
#define LVP_ON               0xFFFF 
// Single-Supply ICSP disabled
#define LVP_OFF              0xFFFB 
// Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit
// ICPORT enabled
#define ICPRT_ON             0xFFDF 
// ICPORT disabled
#define ICPRT_OFF            0xFFFF 
// Extended Instruction Set Enable bit
// Instruction set extension and Indexed Addressing mode enabled
#define XINST_ON             0xFFBF 
// Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
#define XINST_OFF            0xFFFF 
// Background Debugger Enable bit
// Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
#define DEBUG_OFF            0xFFFF 
// Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
#define DEBUG_ON             0xFF7F 


// Config Register: CONFIG5L
// Code Protection bit
// Block 0 (000800-001FFFh) is not code-protected
#define CP0_OFF              0xFFFF 
// Block 0 (000800-001FFFh) is code-protected
#define CP0_ON               0xFFFE 
// Code Protection bit
// Block 1 (002000-003FFFh) is not code-protected
#define CP1_OFF              0xFFFF 
// Block 1 (002000-003FFFh) is code-protected
#define CP1_ON               0xFFFD 
// Code Protection bit
// Block 2 (004000-005FFFh) is not code-protected
#define CP2_OFF              0xFFFF 
// Block 2 (004000-005FFFh) is code-protected
#define CP2_ON               0xFFFB 
// Code Protection bit
// Block 3 (006000-007FFFh) is not code-protected
#define CP3_OFF              0xFFFF 
// Block 3 (006000-007FFFh) is code-protected
#define CP3_ON               0xFFF7 


// Config Register: CONFIG5H
// Boot Block Code Protection bit
// Boot block (000000-0007FFh) is not code-protected
#define CPB_OFF              0xFFFF 
// Boot block (000000-0007FFh) is code-protected
#define CPB_ON               0xBFFF 
// Data EEPROM Code Protection bit
// Data EEPROM is not code-protected
#define CPD_OFF              0xFFFF 
// Data EEPROM is code-protected
#define CPD_ON               0x7FFF 


// Config Register: CONFIG6L
// Write Protection bit
// Block 0 (000800-001FFFh) is not write-protected
#define WRT0_OFF             0xFFFF 
// Block 0 (000800-001FFFh) is write-protected
#define WRT0_ON              0xFFFE 
// Write Protection bit
// Block 1 (002000-003FFFh) is not write-protected
#define WRT1_OFF             0xFFFF 
// Block 1 (002000-003FFFh) is write-protected
#define WRT1_ON              0xFFFD 
// Write Protection bit
// Block 2 (004000-005FFFh) is not write-protected
#define WRT2_OFF             0xFFFF 
// Block 2 (004000-005FFFh) is write-protected
#define WRT2_ON              0xFFFB 
// Write Protection bit
// Block 3 (006000-007FFFh) is not write-protected
#define WRT3_OFF             0xFFFF 
// Block 3 (006000-007FFFh) is write-protected
#define WRT3_ON              0xFFF7 


// Config Register: CONFIG6H
// Configuration Register Write Protection bit
// Configuration registers (300000-3000FFh) are not write-protected
#define WRTC_OFF             0xFFFF 
// Configuration registers (300000-3000FFh) are write-protected
#define WRTC_ON              0xDFFF 
// Boot Block Write Protection bit
// Boot block (000000-0007FFh) is not write-protected
#define WRTB_OFF             0xFFFF 
// Boot block (000000-0007FFh) is write-protected
#define WRTB_ON              0xBFFF 
// Data EEPROM Write Protection bit
// Data EEPROM is not write-protected
#define WRTD_OFF             0xFFFF 
// Data EEPROM is write-protected
#define WRTD_ON              0x7FFF 


// Config Register: CONFIG7L
// Table Read Protection bit
// Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
#define EBTR0_OFF            0xFFFF 
// Block 0 (000800-001FFFh) is protected from table reads executed in other blocks
#define EBTR0_ON             0xFFFE 
// Table Read Protection bit
// Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
#define EBTR1_OFF            0xFFFF 
// Block 1 (002000-003FFFh) is protected from table reads executed in other blocks
#define EBTR1_ON             0xFFFD 
// Table Read Protection bit
// Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
#define EBTR2_OFF            0xFFFF 
// Block 2 (004000-005FFFh) is protected from table reads executed in other blocks
#define EBTR2_ON             0xFFFB 
// Table Read Protection bit
// Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
#define EBTR3_OFF            0xFFFF 
// Block 3 (006000-007FFFh) is protected from table reads executed in other blocks
#define EBTR3_ON             0xFFF7 


// Config Register: CONFIG7H
// Boot Block Table Read Protection bit
// Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
#define EBTRB_OFF            0xFFFF 
// Boot block (000000-0007FFh) is protected from table reads executed in other blocks
#define EBTRB_ON             0xBFFF

#include <htc.h>
#include <string.h>
//Chip Settings

// To Be Entered Depending on Your Device

// funtion
void pic_init(void);

char *Stringcopy(unsigned int offset,[COLOR="#FF0000"]const[/COLOR] char *start,[COLOR="#FF0000"]const[/COLOR] char *end);
char SMSin[200]={" +CMGL: 4,\"REC UNREAD\",\"+855977105636\",\"\",\"12/02/08,11:14:47+28\" >Engine Stop"};


main()
{
while(1)
{
while(PORTBbits.RB0==1)
{
	Stringcopy(2,"+",",");
	while(PORTBbits.RB0==1);
}

}
}

char * Stringcopy(unsigned int offset,[COLOR="#FF0000"]const[/COLOR] char *start, [COLOR="#FF0000"]const[/COLOR] char *end)
{
	char * result = NULL;
	result = strtok( SMSin, start );

	if( result != NULL )
	{
		result = strtok( NULL, end );
	}
	return result;
}

void pic_init(void)
{
	TRISA= 0b00000000;
	TRISB= 0b00000000;
	TRISC= 0b10000000;

	PORTA= 0b00000000;
	PORTB= 0b00000000;
	PORTC= 0b00000000;

	ADCON1= 0b00000110;
	INTCON= 0b11000000;
	PIE1= 0b00100000; //Enable RX interrupt
}