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    -= Gate Count Calculation from the Verilog Code =-

    Hi All,
    How is it possible to calculated the Gate Count just from the Verilog Code? How should it be calculated?
    Are there any free tools, which can do such job?
    Thank you!

    ---------- Post added 18-02-12 at 00:00 ---------- Previous post was 17-02-12 at 23:55 ----------

    What is "Gate Factor"? How could it be calculated and used? Thank you!

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    Re: -= Gate Count Calculation from the Verilog Code =-

    you should synthesize the code first to know the the area of the whole design. Then divide the whole area by the area of 2 input NAND gate. This will give you the gate count of the design in terms of NAND2 gate equivalents. This is the most commonly used



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    Re: -= Gate Count Calculation from the Verilog Code =-

    No, I mean how to estimate a Gate Count just from the RTL Code.
    What tools (besides the Digign Compiler) could do this job? Can Lint help?



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    Re: -= Gate Count Calculation from the Verilog Code =-

    you could count the number of flop you have in your design (in sync process), multiple by 2 to have the area of logic included and divide by the AND gate area, you will rougtly your estimations.


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    Re: -= Gate Count Calculation from the Verilog Code =-

    Thank you rca!
    Now how to estimate the area increase due to routing?
    Thank you!



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    Re: -= Gate Count Calculation from the Verilog Code =-

    rougly 75-80% std cell density


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    Re: -= Gate Count Calculation from the Verilog Code =-

    Quote Originally Posted by rca View Post
    rougly 75-80% std cell density
    Okay, thank you!

    And how much area does the BIST add?

    What are the advantages and disadvantages of testing the Memory using Software? Is it done on the Tester?

    Thank you!



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    Re: -= Gate Count Calculation from the Verilog Code =-

    the bist area is very dependent of the memory type.
    advantage of software:
    you could change the algo.
    could be done develop after tapeout
    less gate (power...)

    disadvantage:
    less parallelisme.
    could be execute at each power up, or need to be on the rom code...



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    Re: -= Gate Count Calculation from the Verilog Code =-

    rca dude where did you get the following. multiplying by 2 is not making sense to me. Could you please explain
    "
    you could count the number of flop you have in your design (in sync process), multiple by 2 to have the area of logic included and divide by the AND gate area, you will rougtly your estimations.
    "



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    Re: -= Gate Count Calculation from the Verilog Code =-

    Quote Originally Posted by rca View Post
    the bist area is very dependent of the memory type.
    advantage of software:
    you could change the algo.
    could be done develop after tapeout
    less gate (power...)

    disadvantage:
    less parallelisme.
    could be execute at each power up, or need to be on the rom code...
    Thanks rca!

    Why SW should test memories on each power up? Is it not enough to check it once during the production? Can it mask the damaged memory cells or it depends on the running operation system?

    As for the BIST, does it also run its tests on each power up or just during the production only?

    Thank you in advance for your reply!



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    Re: -= Gate Count Calculation from the Verilog Code =-

    Some system required to check the memory at each power up, for safety system for example to guaranty the perfect functionality
    Normally at test production is enough.


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    Re: -= Gate Count Calculation from the Verilog Code =-

    Great rca! Thanks for your comments!



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    Re: -= Gate Count Calculation from the Verilog Code =-

    For previous projects we seen this empiric ratio for std cell 1/3 for flop 2/3 for combinational logic for std cell area, memories & pads & others macros need to be added separetly.

    So my previous indication need to be changed.


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