Distributed ram warning/error

Hi guys,

I have a problem regarding RAM. What I have to make is 76800(240 x 320) cells of 3 bit- memory.
Every cell can be accessed using either the W_ADDR(write) or R_ADDR(read) lines.
I use so many cells, because it will make it easier for me to access each cell individually.

When I synthesize, I get the following warning:
XST:790: line 50: Index values doe not match array range, simulation mismatched
and
Contents of array<background> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.

Line 50 is bold. The same goes for the line where sprites gets a value.

I use signal RD_ADDR_REG because my teacher says that if you don't use it, the memory will be placed using LUTS and not the block RAM.

Do you happen to have any idea why the array sizes don't match?(I've checked the sizes many times)





-- Description: RAM memory used in GPUdrive project. It reads data from a block of RAM
-- The data stored in RAM_MEM will be displayed by GPU.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RAM_MEM is
generic ( Y : integer := 240;
X : integer := 320;
RGB : integer := 3;
--The integers defined below are directly linked with the length of the integers above!!--
X_size : integer := 9;
Y_size : integer := 8;
RGB_S: integer := 3
);
port (CLK : in std_logic;
--First bit from left to right: Foreground, Sprites
Reg_Select : in std_logic_vector(1 downto 0);
Write_en : in std_logic;
W_addr : in std_logic_vector(((X_size + Y_size) -1) downto 0);
R_addr : in std_logic_vector(((X_size + Y_size) -1) downto 0);--For 76800 Adresses
data_in : in std_logic_vector((RGB_S -1) downto 0);
data_out : out std_logic_vector((RGB_S -1) downto 0));
end RAM_MEM;

architecture Behavioral of RAM_MEM is
--RAM for Colordata
type ramtype is array (((X_size + Y_size )-1) downto 0) of std_logic_vector((RGB_S -1) downto 0);

signal background : ramtype;
--RAM forsprites
signal sprites : ramtype;

signal RD_ADDR_REG : std_logic_vector(((X_size + Y_size )-1) downto 0);
begin

process(CLK)
begin
if rising_edge(CLK) then
--WRITE---
if write_en = '1' then
--background
if reg_select = "10" then background(to_integer(unsigned(W_addr))) <= data_in
--Sprites--
else sprites(to_integer(unsigned(W_addr))) <= data_in;
end if;
RD_ADDR_REG <= R_addr;
--READ----
else
--Background
if reg_select = "10" then data_out<= background(to_integer(unsigned(RD_ADDR_REG)));
--Sprites
else data_out <= sprites(to_integer(unsigned(RD_ADDR_REG)));
end if;
end if;
end if;
end process;
end architecture;


Thank you for your time and help!

your ramtype is declared only having 17 addressable locations, while the addresses can access 2**17. I think you meant to write:

type ramtype is array (2** ((X_size + Y_size )-1) downto 0) of std_logic_vector((RGB_S -1) downto 0);