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What are the major factors that decide pcb is of high speed?

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soppcb

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rise time is the most important major? What's your idea?

Jack
soppcbtech at gmail dot com
 

Rise Time determines the spectral (harmonic) content of the square waves, the faster the rise time the higher frequencys of the harmonics, the rise time also determines the electrical length of a line, which allows us to determine whether it should be atreated as a transmission line or not. Most devices these days seem to have aggressive current drive, and thus high rise times.
A quote from National
For calculation purposes, you should understand the concept of electrical length (l). Electrical length is defined as the distance that a signal can travel in an electrical medium during the time that it takes for one rise or fall time, whichever is longer. Using the concept of electrical length, the general rule of the previous paragraph can be rephrased as follows: If the physical length of a wire or electrical interconnect is greater than 1/6 of the electrical length of a signal propagating on that wire, the system must be analyzed as a transmission line. Velocity is defined as the rate at which an electrical wave propagates in the transmission medium. Using this value you can calculate electrical length in one of the following ways:

Full Notes:
Proper Termination for High-Speed Digital I/O Applications - Developer Zone - National Instruments

My guidlines are to treat EVERY digital signal as critical and always use best practice design, some signals demand extra special TLC, such as DDR memory iinterface, Ethernet etc
 
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    soppcb

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Hello, Marce, thanks for your clear explaination.
Jack
soppcbtech at gmail dot com

Rise Time determines the spectral (harmonic) content of the square waves, the faster the rise time the higher frequencys of the harmonics, the rise time also determines the electrical length of a line, which allows us to determine whether it should be atreated as a transmission line or not. Most devices these days seem to have aggressive current drive, and thus high rise times.
A quote from National


Full Notes:
Proper Termination for High-Speed Digital I/O Applications - Developer Zone - National Instruments

My guidlines are to treat EVERY digital signal as critical and always use best practice design, some signals demand extra special TLC, such as DDR memory iinterface, Ethernet etc
 

Now to add a bit of spice to life, which Tr, 10-90% or 20-80%, and why are there two figures used for Tr???:smile:
 

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