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What's the precision of timescale 1ns?

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timescale 1ns/1ps, the simulation time unit is 1ns and time precision is 1ps. If just as timescale 1ns, what's the default time precision? Is it related to simulation enviroment and tools?

Thanks.
 

It means when you put lets say #5 in testbench, it means 5ns

and precision of 1ps means 5.0005 ns will be represented as 5ns, 5.005 ns will be represented as 5.005 ns


Others members can correct me if i am wrong
 

timescale 1ns/1ps means whatever time you mention in your test bench will be taken in " ns" , like # 10 as 10 ns.

Precision of 1ps means you can have " # 0.001 " as " # 0.001 ns/1ps " , but " # 0.00013 " means 0 ns.
 
Last edited:
`timescale 1ns/1ps means that all the delays that follow (like #5) are interpreted to be in nanoseconds and any fractions will be rounded to the nearest picosecond. However, all delays are represented as integers. The simulator knows nothing about seconds or nanoseconds, only unit-less integers.

It might help to understand that Verilog is defined with discrete event-driven simulation semantics. That means simulation time is defined as an integer, and all signal changes (events) scheduled for a later time are put into queues. A queue for a discrete time in the future is created as soon as an event needs to be scheduled for that time. As soon as all the events for the current time are finished, the simulator looks for the next time queue where an event is scheduled, advances the current time to that next time, and the process repeats until there is nothing left to do, or it executes a $finish. Time is discrete because the simulator only executes the times where events are scheduled, and skips over everything else.

In order to synchronize the scheduling of events across different modules with different timescales and precisions, the simulator picks the smallest time precision across the entire design and assigns that the value of 1 time unit. If the smallest precision was 10ps, that becomes the global value of 1 time unit. So if there were a module with a timescale of 1ns/1ns and there was a delay of #12.3, that would be rounded to 12ns and then scaled to an integer of 1200. (1200x10ps= 12ns)
 
dave

I somewhat disagree with you. Verilog is the HDL language. Event driven simulation or cycle based simulation are implementation of the verilog language to make a simulator.

Verilog is not defined by event-driven simulation semantics. Its the simulation that is defined with event-driven simulation semantics.



(The other problem is that i and other members can not send you private messaage :{ . Anyway that is your choice)
 

I think you have it backwards. You can read the the text of the LRM that you just posted (which is a copyright violation, BTW), or the current SystemVerilog LRM.

1364-2001 said:
5.2 Event simulation
The Verilog HDL is defined in terms of a discrete event execution model. [...] In addition, Verilog HDL simulators are free to use different algorithms than those described in
this section, provided the user-visible effect is consistent with the reference model.
Click to expand...
 
Thanks for letting me know. LRM is removed.
 

If your code has not delays in it, then it does not matter.

If your code does have delays, then most simulators will pick a default timescale for you. But I think that is a very bad idea, you should always specify the scale.

SystemVerilog has an improvement that lets you specify the timescale when you write the delay, i.e. #10ns.

Dave
 
Let me also ask this question as i am not sure about it.

Does only testbench need to have timescale defined or other modules can also have timescale defined in them?


Secondly, can there be different timescales for different modules? (perhaps not) but want to double check?

I think i should spend sometime reading the verilog standard
 

Yes, different modules can have different timescales. Since `timescale is a compiler directive, all of the modules that follow that compiler directive use that timescale. So if some modules do, and other modules don't put a `timescale directive in front the module declaration, it gets the timescale that was put in front of the previous module. So if there are different timescales and you change the order of compilation of your modules, the modules without a `timescale directive may get a different timescale.

Again, SystemVerilog solved this problem by allowing you to put the timescale right on the delay number, as well as providing a timeunit statement that applies to a specific scope and is not a compiler directive.
 
Hi dave , Its a silly question , but need to ask . Is 1ns/1ps fixed i.e. can't we take it as 2ns/2ps , 3ns/3ps etc. etc , or is it compulsory that we should give 'timescale values in 1ns/1ps , 10ns/10ns , 100ns/100ps i.e. in multiple of 10 only .... n one more thing that if i take 'timescale 10ns/10ps , then how #12.3 will b rounded to ? little confused about it , yesterday i screwed synopsys interview bcoz of silly mistakes .
dave_59 said:
`timescale 1ns/1ps means that all the delays that follow (like #5) are interpreted to be in nanoseconds and any fractions will be rounded to the nearest picosecond. However, all delays are represented as integers. The simulator knows nothing about seconds or nanoseconds, only unit-less integers.

It might help to understand that Verilog is defined with discrete event-driven simulation semantics. That means simulation time is defined as an integer, and all signal changes (events) scheduled for a later time are put into queues. A queue for a discrete time in the future is created as soon as an event needs to be scheduled for that time. As soon as all the events for the current time are finished, the simulator looks for the next time queue where an event is scheduled, advances the current time to that next time, and the process repeats until there is nothing left to do, or it executes a $finish. Time is discrete because the simulator only executes the times where events are scheduled, and skips over everything else.

In order to synchronize the scheduling of events across different modules with different timescales and precisions, the simulator picks the smallest time precision across the entire design and assigns that the value of 1 time unit. If the smallest precision was 10ps, that becomes the global value of 1 time unit. So if there were a module with a timescale of 1ns/1ns and there was a delay of #12.3, that would be rounded to 12ns and then scaled to an integer of 1200. (1200x10ps= 12ns)
Click to expand...
 

Timescale/precision must be a power of 10. Probably a remnant from a time when voltmeters had a sliding decimal point scale. In practice, I rarely see anything other than "1" for a timescale.

With a timescale/precision of 10ns/10ps,#12.3 means 123ns. If you had #12.123, that would mean 12.12ns because the 3ps would be rounded off. If 10ps was the smallest time precision in your design, that delay would then be scaled to the integer 1212.
 

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